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freescale semiconductor data sheet, technical data i.mx27 and i.mx27l package information plastic package case 1816-01 (mapbga?404) case 1931-04 (mapbga-473) ordering information see ta b l e 1 on page 4 for ordering information. document number: mcimx27ec rev. 1.3, 12/2008 ? freescale semiconductor, inc., 2007, 2008. all rights reserved. this document contains information on a new product. specifications and information herein are subject to change without notice. 1 introduction the i.mx27 and i.mx27l (mcimx27/mx27l) multimedia applications processors represents the next step in low-power, high-performance application processors. unless otherwise specified, the material in this data sheet is applicable to both the i.mx27 and i.mx27l processors and referred to singularly throughout this document as i.mx27. the i.mx27l does not include the following features: ata-6 hdd interface, memory stick pro, vpu: mpeg-4/ h.263/h.264 hw encoder/decoder, and emma (prp processing, csc, deblock, dering). based on an arm926ej-s? microprocessor core, the i.mx27/27l processor provides the performance with low-power consumption required by modern digital devices such as the following: ? feature-rich cellular phones ? portable media players and mobile gaming machines ? personal digital assistants (pdas) and wireless pdas i.mx27 and i.mx27l data sheet multimedia applications processor contents 1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3. ordering information . . . . . . . . . . . . . . . . . . . . . . 4 2. functional description and application information . . . . 4 2.1. arm926 microprocessor core platform . . . . . . . . 4 2.2. module inventory . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3. module descriptions . . . . . . . . . . . . . . . . . . . . . . . 9 3. signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.1. power-up sequence . . . . . . . . . . . . . . . . . . . . . . 35 3.2. emi pins multiplexing . . . . . . . . . . . . . . . . . . . . . 36 4. electrical characteristics . . . . . . . . . . . . . . . . . . 40 4.1. i.mx27/imx27l chip-level conditions . . . . . . . . 40 4.2. module-level electrical specifications . . . . . . . . 43 4.3. timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . 54 5. package information and pinout . . . . . . . . . . . . . . . . 105 5.1. full package outline drawing (17 mm 17 mm ) 105 5.2. pin assignments (17 mm 17 mm) . . . . . . . . . 106 5.3. full package outline drawing (19 mm 19 mm ) 124 5.4. pin assignments (19 mm 19 mm) . . . . . . . . . 125 6. product documentation . . . . . . . . . . . . . . . . . . . . . . . 144 7. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
i.mx27 and i.mx27l data sheet, rev. 1.3 2 freescale semiconductor introduction ? portable dvd players ? digital cameras the i.mx27/mx27l processor features the advanced and power-efficient arm926ej-s core operating at speeds up to 400 mhz, and is optimized for minimal power consumption using the most advanced techniques for power saving (for example, dptc, power gating, and clock gating). with 90 nm technology and dual vt, the i.mx27/mx27l device provides the optimal performance vs. leakage current balance. the performance of the i.mx27/mx27l processors are both boosted by an on-chip cache system, and features peripheral devices, such as an mpeg-4, h.263, an h.264 video codec (up to d1?720 x 486?@ 30 fps), lcd, emma_lt, and cmos sensor interface controllers. the i.mx27/mx27l processors supports connections to various types of external memories, such as 266-mhz ddr, nand flash, nor flash, sdram, and sram. the i.mx27/mx27l devices can be connected to a variety of external devices usi ng technology, such as high-speed usbotg 2.0, the advanced technology attachment (ata), multimedi a/secure data (mmc/sdio), and compactflash. note the i.mx27l does not support the ata-6 hdd interface. 1.1 features the mx27/mx27l processors are targeted for video and voice over-ip (v2ip) and smart remote controllers. it also provides low-power solutions for any high-performance and demanding multimedia and graphics applications. the systems include the following features: ? multi-standard video codec (i.mx27 only) ? mpeg-4 part-ii simple profile encoding/decoding ? h.264/avc baseline profile encoding/decoding ? h.263 p3 encoding/decoding ? multi-party call: one stream encoding and two streams decoding simultaneously ? multi-format: encodes mpeg-4 bitstream, and decodes h.264 bitstream simultaneously ? on-the-fly video processing that reduces system memory load (for example, the power-efficient viewfinder applica tion with no involvement of either the memory system or the arm cpu) ? advanced power management (i.mx27/27l) ? dynamic process and temperature compensation ? multiple clock and power domains ? independent gating of power domains ? multiple communication and expansion ports
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 3 introduction 1.2 block diagram figure 1 shows the i.mx27 simplified interface block diagram. figure 1. i.mx27/mx27l simplified interface block diagram application processor domain (ap) ap peripherals arm926 vram ddr/ sdram nor/nand flash audio/power management arm926ej-s l1 i/d cache camera platform bluetooth wlan usbotg mmc/sdio keypad xvr jtag irda xvr access conn. lcd display timers audmux gpt (6) pwm rtc gpio wdog 1-wire i 2 c (2) cspi (3) sdhc (3) kpp jtag ahb switch fabric irom ssi (2) security sahara2 rtic scc crm m3if lcdc slcdc csi usbotg hs mshc fec dma emma-lt video codec ata 10/100 eth xvr sdramc weim nfc pcmcia/cf aitc etm9 iim uart (6) note: the i.mx27l does not support the following: ? ata-6 hdd interface ?memory stick pro ? vpu: mpeg-4/.263/h.264 hw encoder/decoder ? emma (prp processing, csc, deblock, dering)
i.mx27 and i.mx27l data sheet, rev. 1.3 4 freescale semiconductor functional description and application information 1.3 ordering information table 1 provides ordering information for the mapbga, lead-free packages. 2 functional description and application information 2.1 arm926 microprocessor core platform the arm926 platform consists of the arm926ej-s processor, etm9, etb9, a 6 3 multi-layer ahb crossbar switch (max), and a ?primary ahb? complex. ? the instruction bus (i-ahb) of the arm926ej-s processor is connected directly to max master port 0. ? the data bus (d-ahb) of the arm926ej-s processor is connected directly to max master port 1. four alternate bus master interfaces are connected to max master ports 2?5. three slave ports of the max are ahb-lite compliant buses. slave port 0 is designated as the ?primary? ahb. the primary ahb is internal to the platform and has five slaves connected to it: the aitc interrupt module, the mctl memory controller, and two aipi peripheral interface gaskets. slave ports 1 and 2 of the max are referred to as ?secondary? ahbs. each of the secondary ahb interfaces is only accessible off platform. the arm926ej-s processor supports the 32-bit and 16-bit arm thumb instruction sets, enabling the user to trade off between high performance and hi gh-code density. the arm926ej-s processor includes features for efficient execution of java byte codes, providing java performance similar to the just-in-time (jit) compiler?which is a type of java comp iler?but without the associated code overhead. the arm926ej-s processor supports the arm debug architecture and includes logic to assist in both hardware and software debugging. the arm926ej-s processor has a harvard cached architecture and provides a complete high-performance processor subsystem, including the following: ? an arm9ej-s integer core ? a memory management unit (mmu) ? separate instruction and data amba ahb bus interfaces ? etm and jtag-based debug support the arm926ej-s processor provides support for external coprocessors enabling floating-point or other application-specific hardware acceleration to be added. the arm926ej-s processor implements arm architecture version 5tej. table 1. ordering information device temperature package mcimx27vop4a ?20 c to +85 c 1816-01 mcimx27lvop4a ?20 c to +85 c 1816-01 MCIMX27MOP4A ?40 c to +85 c 1931-04 mcimx27lmop4a ?40 c to +85 c 1931-04
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 5 functional description and application information the four alternate bus master ports on the arm926 platform, which are connected directly to master ports of the max, are designed to support connections to multiple ahb masters external to the platform. an external arbitration ahb control module is needed if multiple external masters are desired to share an arm926 platform alternate bus master port. however, the alternate bus master ports on the platform support seamless connection to a single master with no external interface logic required. a primary ahb mux (pahbmux) module performs address decoding, read data muxing, bus watchdog, and other mis cellaneous functions for the primary ahb within the platform. a clock control module (clkctl) is provided to support a power-conscious design methodology, as well as implementation of several clock synchronization circuits. 2.1.1 memory system the arm926ej-s complex includes 16-kbyte instru ction and 16-kbyte data caches. the embedded 45-kbyte sram (vram) can be used to avoid external memory accesses or it can be used for applications. there is also a 24-kbyte rom for bootstrap code. 2.2 module inventory table 2 shows an alphabetical listing of the modules in the i.mx27/mx27l multimedia applications processors. a cross-reference to each module?s secti on and page number goes dir ectly to a more detailed module description for additional information. table 2. digital and analog modules block mnemonic block name functional grouping brief description section/ page 1-wire ? 1-wire interface connectivity peripheral the 1-wire module provides bi-directional communication between the arm926ej-s and the add-only-memory eprom (ds2502). the 1-kbit eprom is used to hold information about battery and communicates with the arm926 platform using the ip interface. 2.3.1/9 aipi ahb-lite ip interface module bus control the aipi acts as an interface between the arm advanced high-performance bus lite. (ahb-lite) and lower bandwidth peripherals that conforms to the ip bus specification, rev 2.0. 2.3.2/10 aitc arm9ej-s interrupt controller bus control aitc is connected to the primary ahb as a slave device. it generates the normal and fast interrupts to the arm926ej-s processor. 2.3.3/10 arm926ejs arm926ej-s cpu the arm926ej-s (arm926) is a member of the arm9 family of general-purpose microprocessors targeted at multi-tasking applications. 2.3.4/10 ata advanced technology(at) attachment connectivity peripheral the ata block is an at attachment host interface. it interfaces with ide hard disc drives and atapi optical disc drives. 2.3.5/11 audmux digital audio multiplexer multimedia peripheral the audmux interconnections allow multiple, simultaneous audio/voice/data flows between the ports in point-to-point or point-to-multipoint configurations. 2.3.6/11
i.mx27 and i.mx27l data sheet, rev. 1.3 6 freescale semiconductor functional description and application information crm clock and reset module clock and reset control the crm generates clock and reset signals used throughout the i.mx27/mx27l processors and also for external peripherals. 2.3.7/12 csi cmos sensor interface multimedia interface the csi is a logic interface which enables the i.mx27/mx27l processors to connect directly to external cmos sensors and a ccir656 video source. 2.3.8/12 cspi configurable serial peripheral interface (x3) connectivity peripheral the i.mx27/mx27l processors have three cspi modules. cspi is equipped with two data fifos and is a master/slave configurable serial peripheral interface module, allowing the i.mx27/mx27l processors to interface with both external spi master and slave devices. 2.3.9/13 dmac direct memory access controller standard system resource the dmac of the i.mx27/mx27l processors provides 16 channels supporting linear memory, 2d memory, fifo and end-of-burst enable fifo transfers to support a wide variety of dma operations. 2.3.10/13 emma_lt emma_lt h/w accelerator functions emma_lt consists of a preprocessor and postprocessor, and provides video acceleration. the prp and pp can be used for generic video pre and post processing such as scaling, resizing, and color space conversions. 2.3.11/13 emi external memory interface memory interface (emi) the emi includes ? multi-master memory interface (m3if) ? enhanced sdram/mddr memory controller (esdramc) ? pcmcia memory controller (pcmcia) ? nand flash controller (nfc) ? wireless external interface module (weim) ? esdramc enhanced sdram controller external memory interface the esdramc provides interface and control for synchronous dram memories for the system. 2.3.12/15 fec fast ethernet controller connectivity peripheral the fec performs the full set of ieee 802.3/ethernet csma/cd media access control and channel interface functions. the fec supports connection and functionality for the 10/100 mbps 802.3 media independent interface (mii). it requires an external transceiver (phy) to complete the interface to the media. 2.3.13/15 gpio general purpose i/o module pins the gpio provides 32 bits of bidirectional, general purpose i/o. this peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. 2.3.14/16 gpt general purpose timer timer peripheral the gpt is a multipurpose module used to measure intervals or generate periodic output. 2.3.15/16 i 2 cinter ic communication connectivity peripheral the i 2 c provides serial interface to control the sensor interface and other external devices. data rates of up to 100 kbits/s are supported. 2.3.16/17 table 2. digital and analog modules (continued) block mnemonic block name functional grouping brief description section/ page
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 7 functional description and application information iim ic identification module security the iim provides an interface for reading?and in some cases, programming, and overriding identification and control information stored in on-chip fuse elements. contact your freescale semiconductor sales office or distributor for additional information on scc, rtic, iim, sahara2 2.3.17/17 jtagc jtag controller debug the jtagc provides debug access to the arm926 core, built-in self-test (bist), and boundary scan test control. 2.3.18/17 kpp keypad port connectivity peripheral the kpp is used for key pad matrix scanning or as a general purpose i/o. this peripheral simplifies the software task of scanning a keypad matrix. 2.3.19/17 lcdc liquid crystal display controller multimedia interface the lcdc provides display data for external gray-scale or color lcd panels. 2.3.20/17 m3if multi-master memory interface external memory interface the m3if controls memory accesses from one or more masters through different port interfaces to different external memory controllers esdctl/mddrc, pcmcia, nfc, and weim. 2.3.21/18 max multi-layer ahb crossbar switch bus control the arm926ej-s processor?s instruction and data buses and all alternate bus master interfaces arbitrate for resources via a 6 3 max. there are six fully functional master ports (m0?m5) and three fully functional slave ports (s0?s2). the max is uni-directional. all master and slave ports are ahb-lite compliant. 2.3.22/18 mshc memory stick host controller connectivity peripheral the mshc is placed in between the aipi and the customer memory stick to support data transfer from the i.mx27 device to the customer memory stick. note: the i.mx27l does not support the mshc feature 2.3.23/19 nfc nand flash controller external memory interface the nfc is a submodule of emi. the nfc implements the interface to standard nand flash memory devices. 2.3.24/19 pcmcia personal computer memory card international association external memory interface the pcmcia host adapter module provides the control logic for pcmcia socket interfaces, and requires some additional external analog power switching logic and buffering. 2.3.25/20 pll phase lock loop clock and reset control the two dplls provide clock generation in digital and mixed analog/digital chips designed for wireless communication and other applications. 2.3.26/20 pwm pulse-width modulator timer peripheral the pwm has a 16-bit counter and is optimized to generate sound from stored sample audio images. it can also generate tones. 2.3.27/20 table 2. digital and analog modules (continued) block mnemonic block name functional grouping brief description section/ page
i.mx27 and i.mx27l data sheet, rev. 1.3 8 freescale semiconductor functional description and application information rtc real time clock timer peripheral the rtc module provides a current stamp of seconds, minutes, hours, and days. alarm and timer functions are also available for programming. the rtc supports dates from the year 1980 to 2050. 2.3.28/20 rtic run-time integrity checkers security the rtic ensures the integrity of the contents of the peripheral memory and assists with boot authentication. contact your freescale semiconductor sales office or distributor for additional information on scc, rtic, iim, sahara2 2.3.29/21 sahara2 symmetric/ asymmetric hashing and random accelerator security sahara2 is a security co-processor which forms part of the platform independent security architecture (pisa), and can be used on cell phone baseband processors or wireless pdas. contact your freescale semiconductor sales office or distributor for additional information on scc, rtic, iim, sahara2 2.3.30/21 scc security controller module security the scc is a hardware component composed of two blocks?the secure ram module, and the security monitor. the secure ram provides a way of securely storing sensitive information. the security monitor implements the security policy, checking algorithm sequencing, and controlling the secure state. contact your freescale semiconductor sales office or distributor for additional information on scc, rtic, iim, sahara2 2.3.31/21 sdhc secured digital host controller connectivity peripheral the sdhc controls the mmc (multimediacard), sd (secure digital) memory, and i/o cards by sending commands to cards and performing data accesses to and from the cards. 2.3.32/21 slcdc smart liquid crystal display controller multimedia interface the slcdc module transfers data from the display memory buffer to the external display device. 2.3.33/22 ssi synchronous serial interface multimedia peripheral the ssi is a full-duplex, serial port that allows the chip to communicate with a variety of serial devices, such as standard codecs, digital signal processors (dsps), microprocessors, peripherals, and popular industry audio codecs that implement the inter-ic sound bus standard (i 2 s) and intel ac97 standard. 2.3.34/22 uart universal asynchronous receiver/ transmitter connectivity peripheral the uart provides serial communication capability with external devices through an rs-232 cable or through use of external circuitry that converts infrared signals to electrical signals (for reception) or transforms electrical signals to signals that drive an infrared led (for transmission) to provide low speed irda compatibility. 2.3.35/23 table 2. digital and analog modules (continued) block mnemonic block name functional grouping brief description section/ page
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 9 functional description and application information 2.3 module descriptions this section provides a brief text description of all the modules included in the i.mx27/mx27l devices, arranged in alphabetical order. 2.3.1 1-wire module the 1-wire module provides bi-directional communica tion between the arm926 core and the add-only memory eprom, ds2502. the 1-kbit eprom holds information about the battery and communicates with the arm926 platform using the ip interface. through the 1-wire interface, the arm926 acts as the bus master while the ds2502 device is the slave. the 1-wire peripheral does not trigger interrupts; hence it is necessary for the arm926 to poll the 1-wire to manage the module. the 1-wire uses an external pin to connect to the ds2502. timing requirements are met in hardware with the help of a 1 mhz clock. the clock divider generates a 1 mhz clock that is used as a time reference by the state machine. timing requirements are crucial for proper operation, and the 1-wire state machine and the internal clock provide the necessary signal. the clock must be configured to approximately 1 mhz. you can then set the 1-wire register to send and receive bits over the 1-wire bus. usb universal serial bus?2 host controllers and 1 otg (on-the-go) connectivity peripherals the i.mx27/mx27l processors provide two usb host controllers and one usbotg of which: ? usb host 1 is designed to support transceiverless connection to the on-board peripherals in low speed and full speed mode, and connection to the ulpi (utmi+low-pin court) and legacy full speed transceivers ? usb host 2 is designed to support transceiverless connection to the cellular modem baseband processor ? the usbotg controller offers hs/fs/ls capabilities in host mode and hs/fs in device mode. in host mode, the controller supports direct connection of a fs/ls device (without external hub). in device (bypass) mode, the otg port functions as gateway between the host 1 port and the otg transceiver. 2.3.36/23 video codec video codec hardware acceleration video codec module supports full duplex video codec with 25 fps vga image resolution, integrates h.264 bp, mpeg-4 sp and h.263 p3 video processing standard together. 2.3.39/25 wdog watchdog timer module timer peripheral the wdog module protects against system failures by providing a method for the system to recover from unexpected events or programming errors. 2.3.37/24 weim wireless external interface module external memory interface the wireless external module (weim) handles the interface to devices external to chip, including generation of chip selects, clock and control for external peripherals and memory. it provides asynchronous and synchronous access to devices with sram-like interface. 2.3.38/25 table 2. digital and analog modules (continued) block mnemonic block name functional grouping brief description section/ page
i.mx27 and i.mx27l data sheet, rev. 1.3 10 freescale semiconductor functional description and application information 2.3.2 ahb-lite ip interface module (aipi) the aipi acts as an interface between the arm adva nced high-performance bus lite. (ahb-lite) and lower bandwidth peripherals conforming to the ip bus specification rev 2.0. there are two aipi modules in i.mx27/mx27l processors. the following list summarizes the key features of the aipi: ? all peripheral read transactions require a minimu m of two system clocks (r-ahb side) and all write transactions require a minimum of three system clocks (r-ahb side). ? the aipi supports 8-bit, 16-bit, and 32-bit ip bus peripherals. byte, half word, and full word reads and writes are supported. ? the aipi supports multi-cycle accesses by providing 16-bit to 8-bit peripherals operations and 32-bit to both 16-bit and 8-bit peripherals operations. ? the aipi supports 31 external ip bus periphera ls each with a 4-kbyte memory map (a slot). 2.3.3 arm926ej-s interrupt controller (aitc) the arm926ej-s interrupt controller (aitc) is a 32-bit peripheral that collects interrupt requests from up to 64 sources and provides an interface to the arm926ej-s core. the aitc includes software controlled priority levels for normal interrupts. the aitc performs the following functions: ? supports up to 64 interrupt sources ? supports fast and normal interrupts ? selects normal or fast interrupt request for any interrupt source ? indicates pending interrupt sources via a register for normal and fast interrupts ? indicates highest priority interrupt number via register. (can be used as a table index.) ? independently can enable or disable any interrupt source ? provides a mechanism for software to schedule an interrupt ? supports up to 16 software controlled priority levels for normal interrupts and priority masking ? can single-bit disable all normal interrupts and all fast interrupts. (used in enabling of secure operations.) 2.3.4 arm926ej-s platform the arm926ej-s (arm926) is a member of the arm9 family of general-purpose microprocessors targeted at multi-tasking applications. the arm926 supports the 32-bit arm and 16-bit thumb instructions sets. the arm926 includes features for efficient execution of java byte codes. a jtag port is provided to support the arm debug architecture, along with associated signals to support the etm9 real-time trace module. the arm926ej-s is a ha rvard cached architecture including an arm9ej-s integer core, a memory management unit (mmu), separate instruction and data amba ahb interfaces, separate instruction and data caches , and separate instruction and da ta tightly coupled memory (tcm) interfaces. the arm926 co-processor, instruction tcm, and data tcm interfaces will be tied off within the arm926 platform and will not be available for external connection.
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 11 functional description and application information the arm926ej-s processor is a fully synthesizable macrocell, with a configurable memory system. both instruction and data caches will be 16 kbytes on the plat form. the cache is virtually accessed and virtually tagged. the data cached has physical tags as well. the mmu provides virtual memory facilities which are required to support various platform operating systems such as symbian os, windows ce, and linux. the mmu contains eight fully associative tlb entries fo r lockdown and 64 set associative entries. refer to the arm926ej-s technical reference manual for more information. 2.3.5 advanced technology attachment (ata) the advanced technology attachment (ata) hos t controller complies with the ata/atapi-6 specification. the primary use of the ata host controller is to interface with ide hard disc drives and advanced technology attachment packet interface (atapi ) optical disc drives. it interfaces with the ata device over a number of ata signals. this host controller supports interface protocols as specified in ata/atapi-6 standard, as follows: ? pio mode 0, 1, 2, 3, and 4 ? multiword dma mode 0, 1, and 2 ? ultra dma modes 0, 1, 2, 3, and 4 with bus clock of 50 mhz or higher ? ultra dma mode 5 with bus clock of 80 mhz or higher before accessing the ata bus, the host must program the timing parameters to be used on the ata bus. the timing parameters control the timing on the ata bus. most timing parameters are programmable as a number of clock cycles (1 to 255). some are implied. all of the ata device-internal registers are visible to users, and they are defined as mirror registers in ata host controller. as specified in ata/atapi-6 standard, all the features/functions are implemented by reading/writing to the device?s internal registers. there are basically two protocols that can be active at the same time on the ata bus, as follows: ? the first and simplest protocol (pio mode acc ess) can be started at any time by the arm926 to the ata bus. the pio mode is a slow protocol, mainly intended to be used to program an ata disc drive, but also can be used to transfer data to/from the disc drive. ? the second protocol is the dma mode access. dma mode is started by the ata interface after receiving a dma request from the drive, and only if the ata interface has been programmed to accept the dma request. in dma mode, either multiword-dma or ultra-dma protocol is used on the ata bus. all transfers between fifo and the host ip or dma ip bus are zero wait states transfer, so a high-speed transfer between fifo and dma/host bus is possible. 2.3.6 digital audio mux (audmux) the digital audio mux (audmux) provides progra mmable interconnecting for voice, audio, and synchronous data routing between host serial interf aces?for example, ssi, sap, and peripheral serial interfaces?such as, audio and voice codecs. the audm ux allows audio system connectivity to be modified through programming, as opposed to altering the design of the system into which the chip is designed. the design of the audmux allows multipl e simultaneous audio/voice/data flows between the ports in point-to-point or point-to-multipoint configurations.
i.mx27 and i.mx27l data sheet, rev. 1.3 12 freescale semiconductor functional description and application information included in the audmux are two types of interfaces. the internal ports connect to the processor serial interfaces, and the external ports connect to off-chip audio devices and serial inte rfaces of other processors. a desired connectivity is achieved by configuring the appropriate internal and external ports. the module includes full 6-wire ssi interfaces for asynchronous receive and transmit, as well as a configurable 4-wire (synchronous) or 6-wire (as ynchronous) peripheral interface. the audmux allows each host interface to be connected to any other host or peripheral interface in a point-to-point or point-to-multipoint (network mode). 2.3.7 clock and reset module (crm) the clock and reset module (crm) generates clock and reset signals used throughout the i.mx27/mx27l processor and for external peripherals. it also enables system software to control, customize, or read the status of the following functions: ? chip id ? multiplexing of i/o signals ? i/o driving strength ? i/o pull enable control ? well-bias control ? system boot mode selection ? dptc control 2.3.8 cmos sensor interface (csi) the cmos sensor interface (csi) is a logic interface that enables the i.mx27/mx27l processors to connect directly to external cmos sensors and ccir656 video source. the capabilities of the csi include the following: ? configurable interface logic to support popular cmos sensors in the market ? support traditional sensor timing interface ? support ccir656 video interface, progressive mode for smart sensor, interlace mode for pal and ntsc input ? 8-bit input port for ycc, yuv, bayer, or rgb data ?32 32 fifo storing image data suppor ting core data read and dma data burst transfer to system memory ? full control of 8-bit and 16-b it data to 32-bit fifo packing ? direct interface to emma-lt pre-processing block (prp) - not available on the i.mx27l ? single interrupt source to interrupt controller fro m maskable sensor interrupt sources: start of frame, end of frame, change of field, fifo full ? configurable master clock frequency output to sensor ? asynchronous input logic design. sensor master clock can be driven by either the i.mx27/mx27l processor or by external clock source.
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 13 functional description and application information ? statistic data generation for auto exposure (ae) and auto white balance (awb) control of the camera (for bayer data only) 2.3.9 configurable serial peripheral interface (cspi) the configurable serial peripheral interface (cspi) is used for fast data communication with fewer software interrupts. there are three cspi modules in the i.mx27/mx27l processors, which provide a full-duplex synchronous serial interface, capable of interfacing to the spi master and slave devices. cspi1 and cspi2 are master/slave configurable and include three chip selects to support multiple peripherals. cspi3 is only a master and has one chip-select signal. the transfer continuation function of the cspi enables unlimited length data transfers using 32-bit wi de by 8-entry fifo for both tx and rx data dma support. the cspi ready (spi_rdy) and chip select (ss) c ontrol signals enable fast data communication with fewer software interrupts. when the cspi module is conf igured as a master, it uses a serial link to transfer data between the cspi and an external device. a chip-e nable signal and a clock signal are used to transfer data between these two devices. when the cspi module is configured as a slave, the user can configure the cspi control register to match the external spi master?s timing. 2.3.10 direct memory access controller (dmac) the direct memory access controller (dmac) provides 16 channels to support linear memory, 2d memory, fifo, and end-of-burst enable fifo tran sfers to support a wide variety of dma operations. features include the following: ? support of 16 channels linear memory, 2d memo ry, and fifo for both source and destination ? support of 8-bit, 16-bit, or 32-bit fifo port size and memory port size data transfer ? configurability of dma burst length of up to a ma ximum of 16 words, 32 half-words, or 64 bytes for each channel ? bus utilization control for a channel that is not triggered by dma request ? interrupts that are provided to interrupt handler on bulk data transfer complete or transfer error ? dma burst time-out error to terminate dma cycle when the burst cannot be completed in a programmed timing period ? dedicated external dma request and grant signal ? support of increment, decrement, and no increment for source and destination addressing ? support of dma chaining 2.3.11 enhanced multimedia accelerator light (emma_lt) the enhanced multimedia accelerator light (emma_lt) cons ists of the video pre-processor (prp) and post-processor (pp). in contrast with i.mx21 processor?s components, this emma does not include the video codec. a more powerful video c odec is included as a separate module. note the i.mx27l does not have a emma_lt module.
i.mx27 and i.mx27l data sheet, rev. 1.3 14 freescale semiconductor functional description and application information each module has individual control and configuration registers that are accessed via the ip interface, and are capable of bus mastering the amba bus to i ndependently access system memory without any cpu intervention. this enables each module to be used independently of each other, and enables the pre-processor and post-processor modules to provide acceleration features for other software codec implementations and image processing software. th ese blocks work together to provide video acceleration, and to off-load the cpu from computation intensive tasks. the prp and pp can be used for generic video pre- and post-processing, such as scaling, resizing, and color space conversions. a 32-bit-to-64-bit ahb gasket is used to convert a pr p ahb bus from a 32-bit to 64-bit protocol. a bypass function is implemented to bypass this 64-bit gasket if it is not needed. emma_lt supports the following image/video processing features: ? pre-processor: ? data input: ? system memory ? private dma between cmos sensor interface module and pre-processor ? data input formats: ? arbitrarily formatted rgb pixels (16 or 32 bits) ? yuv 4:2:2 (pixel interleaved) ? yuv 4:2:0 (iyuv, yv12) ? input image size: 32 32 to 2044 2044 ? image scaling: ? programmable independent ch-1 and ch-2 re sizer. can program to be in cascade or parallel. ? each resizer supports downscaling ratios from 1:1 to 8:1 in fractional steps. ? channel-1 output data format ? channel 1 ? rgb 16 and 32 bpp ? yuv 4:2:2 (yuyv, yvyu, uyvy, vyuy) ? channel-2 output data format ? yuv 4:2:2 (yuyv) ? yuv 4:4:4 ? yuv 4:2:0 (iyuv, yv12) ? rgb data and yuv data format can be generated concurrently ? 32/64-bit ahb bus ? post-processor ? input data: ? from system memory ? input format: ? yuv 4:2:0 (iyuv, yv12) ? image size: 32 32 to 2044 2044
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 15 functional description and application information ? output format: ? yuv 4:2:2 (yuyv) ? rgb16 and rgb32 bpp ?image resize ? upscaling ratios ranging from 1:1 to 1:4 in fractional steps ? downscaling ratios ranging from 1:1 to 2:1 in fractional steps and a fixed 4:1 ? ratios provide scaling between qcif, cif, qvga (320 240, 240 320) 2.3.12 enhanced synchronous dynamic ram controller (esdramc) the enhanced synchronous dynamic ram controller (e sdramc) provides an interface and control for synchronous dram memories for the system. sdram memories use a synchronous interface with all signals registered on a clock edge. a command protocol is used for initialization, read, write, and refresh operations to the sdram, and is generated on the signa ls by the controller (when required due to external or internal requests). it has support for both singl e data rate rams and double data rate sdrams. it supports 64 mbits, 128 mbits, 256 mbits, and 512 mbits, 1 gbit, 2 gbits, four bank synchronous dram by two independent chip selects and with up to 256 mbytes addressable memory per chip select. 2.3.13 fast ethernet controller (fec) the fast ethernet controller (fec) is designed to support both 10 and 100 mbps ethernet/ieee std 802.3? networks. an external tran sceiver interface and transceiver function are required to complete the interface to the media. the fec supports the 10/100 mbps mii and the 10 mbps-only 7-wire interface, which uses a subset of th e mii pins for connection to an external ethernet transceiver. the fec incorporates the following features: ? support for three different ethernet physical interfaces: ? 100-mbps ieee 802.3 mii ? 10-mbps ieee 802.3 mii ? 10-mbps 7-wire interface (industry standard) ? ieee 802.3 full duplex flow control ? programmable max frame length supports ieee std 802.1? vlan tags and priority ? support for full-duplex operation (200 mbps throughput) with a minimum system clock rate of 50 mhz ? support for half-duplex operation (100 mbps throughput) with a minimum system clock rate of 25 mhz ? retransmission from transmit fifo following a collision (no processor bus utilization) ? automatic internal flushing of the receive fifo for runts (collision fragments) and address recognition rejects (no processor bus utilization) ? address recognition ? frames with broadcast address may be always accepted or always rejected
i.mx27 and i.mx27l data sheet, rev. 1.3 16 freescale semiconductor functional description and application information ? exact match for single 48-bit individual (unicast) address ? hash (64-bit hash) check of individual (unicast) addresses ? hash (64-bit hash) check of group (multicast) addresses ? promiscuous mode ? independent dma engine with multiple channels allowing transmit data, transmit descriptor, receive data, and receive descriptor accesses to provide high performance ? independent risc-based controller that pr ovides the following functions in the fec: ? initialization (those internal registers not initialized by the user or hardware) ? high level control of the dma ch annels (initiating dma transfers) ? interpreting buffer descriptors ? address recognition for receive frames ? random number generation for transmit collision backoff timer ? the message information block (mib) in fec main tains counters for a variety of network events and statistics. the counters supported are the rmon (rfc 1757) ethernet statistics group and some of the ieee 802.3 counters. 2.3.14 general purpose i/o module (gpio) the general-purpose input/output (gpio) module provi des dedicated general-purpose pins that can be configured as either inputs or outputs. when it is c onfigured as an output, you can write to an internal register to control the state driven on the output pin. when configured as an input, you can detect the state of the input by reading the state of an internal register. the gpio includes all of the general purpose input/output logic necessary to drive a specific data to the pad and control the direction of the pad using registers in the gpio module. the arm926 is able to sample the status of the corresponding pads by reading the appropriate status register. the gpio s upports up to 32 interrupts and has the ability to identify interrupt edges as well as generate three active high interrupts. 2.3.15 general purpose timer (gpt) the i.mx27/mx27l processors contains six identical 32-bit general purpose timers (gpt) with programmable prescalers and compare and capture regi sters. each timer?s counter value can be captured using an external event, and can be configured to trigger a capture event on the rising or/and falling edges of an input pulse. each gpt can also generate an ev ent on the tout pin, and an interrupt when the timer reaches a programmed value. each gpt has an 11-b it prescaler that provides a programmable clock frequency derived from multiple clock sources, in cluding ipg_clk_32k, ipg_clk_perclk, ipg_clk_perclk/4, and external clock from the tin pin. the counter ha s two operation modes: free-run and restart mode. the gpt can work in low-power mode.
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 17 functional description and application information 2.3.16 inter ic communication (i 2 c) inter ic communication (i 2 c) is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconn ection between devices. this bus is suitable for applications requiring occasional communications over a short distance between many devices. the flexible i 2 c enables additional devices to be connected to the bus for expansion and system development. the i 2 c operates up to 400 kbps dependent on pad loading and timing. (for pad requi rement details, refer to phillips i 2 c bus specification, version 2.1.) the i 2 c system is a true multiple-master bus, including arbitration and collision detection that prevents data corruption if multiple devices attempt to control the bus simultaneously. this feature supports complex a pplications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly-line computer. 2.3.17 ic identification module (iim) the ic identification module (iim) provides an interface for reading and in some cases programming and/or overriding identification and control information stored in on-chip fuse elements. the module supports laser fuses (l-fuses) or electrically-programmable poly fuses (e-fuses) or both. contact your freescale semiconductor sales office or dist ributor for additional information on scc, rtic, iim, sahara2 2.3.18 jtag controller (jtagc) the jtag controller (jtagc) module supports debug access to the arm926 platform and tristate enable of the i/o pads. the overall strategy is to achieve good test and debug features without increasing the pin count and reducing the complexity of i/o muxi ng. the jtag controller is compatible with ieee std 1149.1? standard test access port and boundary scan architecture. 2.3.19 keypad port (kpp) the keypad port (kpp) is designed to interface with a keypad matrix with 2-contact or 3-point contact keys. kpp is designed to simplify the software ta sk of scanning a keypad ma trix. with appropriate software support, the kpp is capable of detecting, debouncing, and decoding one or multiple keys pressed simultaneously in the keypad. the kpp supports up to 8 8 external key pad matrix. its port pins can be used as general purpose i/o. using an open drain design, the kpp includes glitch suppression circuit design, multiple keys, long ke y, and standby key detection. 2.3.20 liquid crystal display controller (lcdc) the liquid crystal display controller (lcdc) provides di splay data for external gray-scale or color lcd panels. the lcdc is capable of supporting black-and-white, gray-scale, passive-matrix color (passive color or cstn), and active-matrix colo r (active color or tft) lcd panels. the lcdc provides the following features: ? configurable ahb bus width (32-bit/64-bit)
i.mx27 and i.mx27l data sheet, rev. 1.3 18 freescale semiconductor functional description and application information ? support for single (non-split) screen monochrome or color lcd panels and self-refresh type lcd panels ? 16 simultaneous gray-scale levels from a palette of 16 for monochrome display ? support for: ? maximum resolution of 800 600 ? passive color panel: ? 4 (mapped to rgb444)/8 (mapped to rgb444)/12 (rgb444) bits per pixel (bpp) ? tft panel: ? 4 (mapped to rgb666)/8 (mapped to rgb666)/12 (rgb444)/16 (rgb565)/18 (rgb666) bpp ? 16 and 256 colors out of a palette of 4096 colors for 4 bpp and 8 bpp cstn display, respectively ? 16 and 256 colors out of a palette of 256 colo rs for 4 bpp and 8 bpp tft display, respectively ? true 4096 colors for a 12 bpp display ? true 64-kbyte colors for 16 bpp ? true 256-kbyte colors for 18 bpp ? 16-bit auo tft lcd panel ? 24-bit auo tft lcd panel 2.3.21 multi-master memory interface (m3if)/m3if-esdctl/mddrc interface the m3if-esdctl/mddrc interface is optimized a nd designed to reduce access latency by generating multiple accesses through the dedicated esdctl/mddr c arbitration (mab) module, which controls the access to and from the enhanced sdram/mddr memory controller. for the other port interfaces, the m3if only arbitrates and forwards the master requests received through the master port gasket (mpg) interface and m3if arbitration (m3a) module toward th e respective memory controller. the masters that interface with the m3if include the arm platform, fec, lcdc, h.264, and the usb. the controllers are the esdctl/mddrc, pcmcia, nfc, and weim. 2.3.22 multi-layer ahb crossbar switch (max) the arm926ej-s processor?s instruction and data buses?and all alternate bus master interfaces?arbitrate for resources via a 6 34 multi-layer ahb crossbar switch (max). there are six (m0?m5) fully functional master ports and three (s0?s2) fully functional slave ports. the max is uni-directional. all master and slave ports are ahb-lite compliant. the design of the crossbar switch enables concurrent tr ansactions to proceed from any master port to any slave port. that is, it is possible for all three slave ports to be active at the same time as a result of three independent master requests. if a pa rticular slave port is simultaneously requested by more than one master port, arbitration logic exists inside the crossbar to allow the higher priority master port to be granted the bus, while stalling the other requestor(s) until that transaction has completed. the slave port arbitration
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 19 functional description and application information schemes supported are fixed, programmable fixed, pr ogrammable default input port parking, and a round robin arbitration scheme. the crossbar switch also monitors the ccm_br input (clock control module bus request), which requests a bus grant from all four slave ports. the priority of ccm_br is programmable and defaults to the highest priority. upon receiving bus grants for all four output ports, the ccm_bg output will assert. at this point, the clock control and reset module (crm) can turn o ff hclk and be assured there are no outstanding ahb transactions in progress. once the crm is granted a port, no other master will r eceive a grant on that port until the crm bus request (ccm_br) negates. 2.3.23 memory stick host controller (mshc) the memory stick host controller (mshc) is locate d between the aipi and the sony memory stick and provides support for data transfers between the i.mx27 processor and the memory stick (ms). the mshc consists of two sub-modules; the mshc gasket and the sony memory stick host controller (smsc). the smsc module, which is the actual memory stick host controller, is compatible with sony memory stick ver 1.x and memory stick pro. the gasket connects the aipi ip bus to the smsc interface to allow communication and data transfers via the ip bus. note the i.mx27l does not include the mshc feature. the mshc gasket uses a reduced ip bus interface that supports the ip bus read/write transfers that include a back-to-back read or write. dma transfers also take place via the ip bus interface. a transfer can be initiated by the dma or the host (through the aipi) response to an mshc dma request or interrupt. the smsc has two dma address modes? a single address mode and a dual address mode. the mshc is set to dual-address mode for transfer s with the dma. in dual-address mode, when the mshc requests a transfer with the dma request (xdr q), the dma will initiate a transfer to the mshc. note details regarding the operation of the mshc module can be found separately in memory stick/memory stick pro host controller ip specification 1.3. 2.3.24 nand flash controller (nfc) nand flash controller (nfc) interfaces standard nand flash devices to the i.mx27/mx27l processors and hides the complexities of accessing the nand flash. it provides a glueless interface to both 8-bit and 16-bit nand flash parts with page size s of 512 bytes or 2 kbytes. its addressing scheme enables it to access flash devices of almost limitless capacity. the 2-kbyte ram buffer of the nand flash is used as the boot ram during a cold reset (if the i.mx27/mx27l device is configured for a boot to be carried out from the nand flash device). after the boot procedure completes, the ram is available as buffer ram. in addition, the nand flash controller provides an x16-bit and x32-bit interface to the ahb bus on the chip side, and an x8/x16 interface to the nand flash device on the external side.
i.mx27 and i.mx27l data sheet, rev. 1.3 20 freescale semiconductor functional description and application information 2.3.25 personal computer memory card international association (pcmcia) the personal computer memory card international association (pcmcia) provides the pcmcia 2.1 standard, which defines the usage of memory and i/o devices as insertable and exchangeable peripherals for personal computers or pdas. examples of thes e types of devices include compactflash and wlan adapters. the pcmcia_if host adapter module provides the control logic for pcmcia socket interfaces, and requires some additional external analog power switching logi c and buffering. the additional external buffers allow the pcmcia_if host adapter module to support one pcmcia socket. the pcmcia_if shares its chip level i/o with the external interface to memory (eim) pins. additional logic is required to multiplex the eim and the pcmcia_if on the same pins. 2.3.26 digital phase lock loop (dpll) two on-chip digital phase lock loop (dplls) pr ovide clock generation in digital and mixed analog/digital chips designed for wireless communi cation and other applications. the dplls produce a high-frequency chip clock signals with a low frequency and phase jitter. 2.3.27 pulse-width modulator (pwm) the pulse-width modulator (pwm) has a 16-bit counter and is optimized to generate sounds from stored sample audio images; it can also generate t ones. the pwm uses 16-bit resolution and a 4 16 data fifo to generate sound. the 16-bit up-counter has a source selectable clock with 4 16 fifo to minimize interrupt overhead. clock-in frequency is controlle d by a 12-bit prescaler for the division of a clock. capable of sound and melody generati on, the pwm has an active-high or active-low configurable output, and can be programmed to be active in low-power and debug modes. the pw m can be programmed to generate interrupts at compare and rollover events. 2.3.28 real time clock (rtc) the real time clock (rtc) module maintains the system clock, provides stopwatch, alarm, and interrupt functions, and supports the following features: ? full clock?days, hours, minutes, seconds ? minute countdown timer with interrupt ? programmable daily alarm with interrupt ? sampling timer with interrupt ? once-per-day, once-per-hour, once-per-mi nute, and once-per-second interrupts ? operation at 32.768 khz or 32 khz, or 38.4 khz (determined by reference clock crystal) the prescaler converts the incoming crystal reference clock to a 1 hz signal, which is used to increment the seconds, minutes, hours, and days tod counters. the alarm functions, when enabled, generate rtc interrupts when the tod settings reach programmed values. the sampling timer generates fixed-frequency interrupts, and the minute stopwatch allows for efficient interrupts on very small boundaries.
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 21 functional description and application information 2.3.29 run-time integrity checker (rtic) the run-time integrity checker (rtic) is one of the security components in the i.mx27/mx27l processors. its purpose is to ensure the integrity of the peripheral memory contents and assist with boot authentication. the rtic has the ability to verify the memory contents during system boot and during run-time execution. if the memory contents at runtime fail to match the hash signature, an error in the security monitor is triggered. contact your freescale semiconductor sales office or dist ributor for additional information on scc, rtic, iim, sahara2 2.3.30 symmetric/asymmetric hashing and random accelerator (sahara2) sahara2 is a security co-processor, it implements encryption algorithms (aes, des, and 3des), hashing algorithms (md5, sha-1, sha_224, and sha-256), stream cipher algorithm (arc4), and a hardware random number generator. contact your freescale semiconductor sales office or dist ributor for additional information on scc, rtic, iim, sahara2 2.3.31 security controller module (scc) the security controller module (scc) is a hardware security component. overall, its primary functionality is associated with establishing a centralized security state controller and hardware security state with a hardware configured, unalterable security policy. contact your freescale semiconductor sales office or dist ributor for additional information on scc, rtic, iim, and sahara2. 2.3.32 secure digital host controller (sdhc) the secure digital host controller (sdhc) controls the multimedia card (mmc), secure digital (sd) memory, and i/o cards by sending commands to cards and performing data accesses to/from the cards. the multimedia card/secure digital host (mmc/sd) module integrates both mmc support along with sd memory and i/o functions. the sdhc is fully compatible with the mmc system specification version 3.0, as well as with the sd memory card specification 1.0, and sd i/o specification 1.0 with 1/4 channel(s). the maximum data rate in 4-bit mode is 100 mbps. the sdhc uses a built-in programmable frequency counter for the sdhc bus, and provides a ma skable hardware interrupt for an sdio interrupt, internal status, and fifo status. it has a pair of 32 16-bit data fifo buffers built in. the multimedia card (mmc) is a universal, low-cost data storage and communication media that is designed to cover a wide area of applications, includi ng, for example, electroni c toys, organizers, pdas, and smart phones. the mmc communication is based on an advanced 7-pin serial bus designed to operate in a low-voltage range. the secure digital card (sd) is an evolution of mmc technology, with two additional pins in the form factor. it is specifically designed to meet the security, capacity, performance, and environment requirements inherent in newly emerging audio and video consumer electronic devices. the physical form
i.mx27 and i.mx27l data sheet, rev. 1.3 22 freescale semiconductor functional description and application information factor, pin assignment, and data transfer protocol are forward-compatible with the multimedia card with some additions. under sd, it can be categorized in to memory and i/o. the memory card invokes a copyright protection mechanism that complies with the se curity of the sdmi standard, which is faster and provides the capability for a higher memory capacity. the i/o card provides high-speed data i/o with low-power consumption for mobile electronic devices. 2.3.33 smart liquid crystal display controller module (slcdc) the smart liquid crystal display controller (slcdc) module transfers data from the display memory buffer to the external display device. direct memory access (dma) transfers the data transparently with minimal software intervention. bus utilization of the dma is controllable and deterministic. as cellular phone displays become larger and more colorful, demands on the processor increase. more cpu power is needed to render and manage the image. the role of the display controller is to reduce the cpu?s involvement in the transfer of data from memo ry to the display device so the cpu can concentrate on image rendering. dma is used to optimize the tr ansfer. embedded control information needed by the display device is automatically read from a second buffer in system memory and inserted into the data stream at the proper time to completely eliminate the cpu?s role in the transfer. a typical scenario for a cellular phone display is to have the display image rendered in main system memory. after the image is complete, the cpu trigge rs the slcdc module to transfer the image to the display device. image transfer is accomplished by burst dma, which steals bus cycles from the cpu. cycle-stealing behavior is programmable so bus use is kept within predefined bounds. after the transfer is complete, a maskable interrupt is generated indicating the status. fo r animated displays, it is suggested that a two-buffer ping-pong scheme be implemented so that the dma is fetching data from one buffer while the next image is rendered into the other. several display sizes and types are used in the various products that use the slcdc. the slcdc module has the capability of directly interfacing to the selected display devices. both serial and parallel interfaces are supported. the slcdc module only supports writes to the display controller. slcdc read operations from the display controller are not supported. 2.3.34 synchronous serial interface (ssi) the synchronous serial interface (ssi) is a full-duplex serial port that allows the chip to communicate with a variety of serial devices. these serial device s can be standard codecs, digital signal processors (dsps), microprocessors, peripherals, and popular i ndustry audio codecs that implement the inter-ic sound bus standard (i2s) and intel ac97 standard. the ssi is typically used to transfer samples in a periodic manner. the ssi consists of independent transmitter and receiver sections with independent clock generation and frame synchronization. the ssi contains independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/external clocks and fram e syncs, operating in master or slave mode. the ssi can work in normal mode operation using frame s ync, and in network mode operation allowing multiple devices to share the port with as many as thirty-two time slots. the ssi provides two sets of transmit and receive fifos. each of the four fifos is 8 24 bits. the two sets of tx/rx fifos can be used in network mode to provide two independent channels for transmission
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 23 functional description and application information and reception. it also has programmable data interf ace modes such as i2s, lsb, and msb aligned and programmable word lengths. other program options include frame sync, clock generation, and programmable i2s modes (master, slave, or normal). oversampling clock, ccm_ssi_clk is available as output from srck in i2s master mode. in addition to ac97 support, the ssi has completely separate clock and frame sync selections for the receive and transmit sections. in the ac97 standard, the clock is taken from an external source and frame sync is generated internally. the ssi also has a programmable internal clock divider and time slot mask registers for reduced cpu overhead (for tx and rx both). 2.3.35 universal asynchronous receiver/transmitter (uart) the i.mx27/mx27l processors contain six uart module s. each uart module is capable of standard rs-232 non-return-to-zero (nrz) encoding format and irda-compatible infrared modes. the uart provides serial communication capability with external devices through an rs-232 cable or through use of external circuitry that converts infrared signals to electrical signals (for reception); or it transforms electrical signals to signals that drive an infrared led (for transmission) to provide low-speed irda compatibility. the uart transmits and receives characters that are either 7 or 8 bits in length (program selectable). to transmit, data is written from the peripheral data bus to a 32-byte transmitter fifo (txfifo). this data is passed to the shift register and shifted serially out on the transmitter pin (txd). to receive, data is received serially from the receiver pin (rxd) and stored in a 32-half-word-deep receiver fifo (rxfifo). the received data is retrieved from the rxfifo on the pe ripheral data bus. the rxfi fo and txfifo generate maskable interrupts as well as dma requests when the data level in each of the fifo reaches a programmed threshold level. the uart generates baud rates based on a programma ble divisor and input clock. the uart also contains programmable auto baud detect ion circuitry to receive 1 or 2 stop bits as well as odd, even, or no parity. the receiver detects framing errors, idle c onditions, break characters, parity errors, and overrun errors. 2.3.36 universal serial bus (usb) the i.mx27/mx27l processors provide three usb ports. the usb module provides high performance usb on-the-go (otg) functionality, compliant with the usb 2.0 specification, the otg supplement, and the ulpi 1.0 low pin count specification. the modul e consists of three independent usb cores, each controlling one usb port. in addition to the usb cores, the usb module provides for transceiverless link (tll) operation on host ports 1 and 2, and provides the ability of routing the otg transceiver interface to host port 1 such that this transceiver can be used to communicate with a usb peripheral connected to host port 1. the usb module has two connections to the cpu bus?one ip -bus connection for register accesses and one ahb-bus connection for the dma transfer of data to and from the fifos. the usb module includes the following features: ? full speed/low speed host only core (host 1) ? transceiverless link logic (tll) for on boa rd connection to a fs/ls usb peripheral
i.mx27 and i.mx27l data sheet, rev. 1.3 24 freescale semiconductor functional description and application information ? bypass mode to route host port 1 signals to otg i/o port ? high speed /full speed/low speed host only core (host 2) ? full speed/low speed interface for serial transceiver ? tll function for direct connection to usb peripheral in fs/ls (serial) operation ? high-speed otg core the usb module has two main modes of operation: normal mode and bypass mode. furthermore, the usb interfaces can be configured for high-speed operation (480 mbps) and/or full/low speed operation (12/1.5 mbps). in normal mode, each usb core controls its corresponding port. in additional to th4e major operational modes, each port can work in one or more modes, as follows: phy mode in phy mode, an extern al serial transceiver is connected to the port. this is used for off-board usb connections. tll mode in tll mode, internal logic is en abled to emulate the functionality of two back-to-back connected transceivers. this mode is typically used for on-board usb connections to usb-capable peripherals. host port 2 supports ulpi and serial transceivers. the otg port requires a transceiver and is intended for off-board usb connections. serial interface mode in serial mode, a serial ot g transceiver must be connected. the port does not support dedicated signals for otg signaling. instead, a transceiver with built-in otg registers must be used. typically, the transceiver registers are accessible over an i2c or spi interface. ulpi mode in this mode, a ulpi transceiver is connected to the port pins to support high-speed off board usb connection. bypass mode bypass mode affects the operation of the otg port and host port 1. this mode is only available when a serial transceiver is used on the otg port, and the peripheral device on port 1 is using a tll connection. bypass mode is activated by setting the bypass bit in the usbcontrol register. in this mode, the usb otg port connections are internally routed to the usb host 1 port, such that the transceiver on the otg port connects to a peripheral usb device on host port 1. the otg core and the host 1 core are disconnected from their ports when bypass is active. low power mode each of the three usb cores has an associated power control module that is controlled by the usb core and clocked on a 32-khz clock. when a usb bus is idle, the transceiver can be placed in low-power mode (suspend), after which the clocks to the usb core can be stopped. the 32-khz low power clock must remain active as it is needed for walk-up detection. 2.3.37 watchdog timer module (wdog) the watchdog timer module (wdog) protects against sy stem failures by providing a method of escaping from unexpected events or programming errors. once the wdog module is activated, it must be serviced by software on a periodic basis. if servicing does not take place, the timer times out. upon a time-out, the wdog timer module either asserts the wdog signal or a system reset signal wdog_rst , depending on
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 25 functional description and application information software configuration. the wdog timer module also generates a system reset via a software write to the watchdog control register (wcr) when there is a detection of a clock monitor event, an external reset, an external jtag reset signal, or if a power-on-reset has occurred. 2.3.38 wireless external interface module (weim) the wireless external interface module (weim) handles the interface to devices external to the chip, including generation of chip selects, clocks and contro ls for external peripherals and memory. it provides asynchronous and synchronous access to devices with an sram-like interface. the weim includes six chip selects for external devices, with two cs signals covering a range of 128 mbytes, and the other four each covering a range of 32 mbytes. the 128-mbyte range can be increased to 256 mbytes when combined with the two signals. the weim offers selectable protection for each chip select as well as programmable data port size. there is a programmable wait-state generator for each chip select and support for big endian and little endian modes of operation per access. 2.3.39 video codec the video codec module is the video processing modul e in the i.mx27 processor. it supports full duplex video codec with 25 fps vga resolution, supports multi-party calls, and inte grates multiple video processing standards, including h.264 bp, mpeg-4 sp, and h.263 p3 (including annex i, j, k, and t), d1 resolution, 30 fps?half-duplex. note the video codec feature is not available on the i.mx27l it has three 64-bit ahb-lite master bus interfaces connecting to the emi, which includes two read channels and one write channel. it s 32-bit ahb-lite master bus is connected to arm platform to access system-internal sram. the video codec module contains three major arch itectural components: video codec processing ip, axi-to-ahb bus protocol transfer module, and a 32-bit to 64-bit ahb master bus protocol transfer module. the video codec module supports following video stream processing features: ? multi-standard video codec ? mpeg-4 part-ii simple profile encoding/decoding ? h.264/avc baseline profile encoding/decoding ? h.263 p3 encoding/decoding ? multi-party call: max processing four ima ge/bitstream encoding and/or decoding simultaneously ? multi-format: for example, encodes mpeg-4 bitstream, and decodes h.264 bitstream simultaneously ? coding tools ? high-performance motion estimation ? single reference frame for both mpeg-4 and h.264 encoding
i.mx27 and i.mx27l data sheet, rev. 1.3 26 freescale semiconductor functional description and application information ? support 16 reference frame for h.264 decoding ? quarter-pel and half-pel accuracy motion estimation ? [+/-16, +/-16] search range ? unrestricted motion vector ? all variable block sizes are supported (in case of encoding, 8 4, 4 8, and 4 4 block sizes are not supported). ? mpeg-4 ac/dc prediction and h.264 intra prediction ? h.263 annex i, j, k(rs = 0 and aso =0), and t are supported. in case of encoding, the annex i and k(rs=1 or aso=1) are not supported. ? cir (cyclic intra refresh)/air (adaptive intra refresh) ? error resilience tools ? mpeg-4 re-synchronize marker and data-p artitioning with rvlc (fixed number of bits/macroblocks between macroblocks) ? h.264/avc fmo and aso ? h.263 slice structured mode ? bit-rate control (cbr and vbr) ? pre/post rotation/mirroring ? 8 rotation/mirroring modes for image to be encoded ? 8 rotation/mirroring modes for image to be displayed ? programmability ? embeds 16-bit dsp processor that is dedicated to processing bitstream and driving codec hardware ? general purpose registers and interrupt generation for communication between system and video codec module
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 27 signal descriptions 3 signal descriptions this section discusses the following: ? identifies and defines all device signals in text, tables, and (as a ppropriate) figures. signals can be organized by group, as applicable. ? contains pin-assignment/contact-connection diagrams , if the sequence of information in the data sheet requires them to be included here. table 3 shows the i.mx27/mx27l signal descriptions. table 3. i.mx27/mx27l signal descriptions pad name function/notes external bus/chip select (emi) a [13:0] address bus signals, shared with sdram/mddr, weim and pcmcia, a[10] for sdram/mddr is not the address but the pre-charge bank select signal. ma10 address bus signals for sdram/mddr a [25:14] address bus signals, shared with weim and pcmcia sdba[1:0] sdram/mddr bank address signals sd[31:0] data bus signals for sdram, mddr sdqs[3:0] mddr data sample strobe signals dqm0?dqm3 sdram data mask strobe signals eb0 active low external enable byte signal that controls d [15:8], shared with pcmcia pc_reg . eb1 active low external enable byte signal that controls d [7:0], shared with pcmcia pc_iord . oe memory output enable?active low output enables external data bus, shared with pcmcia pc_iowr . cs [5:0] chip select?the chip select signals cs [3:2] are multiplexed with csd [1:0] and are selected by the function multiplexing control register (fmcr) in the system control chapter. by default csd [1:0] is selected. dtack is multiplexed with cs4 . cs[5:4] are multiplexed with etmtraceclk and etmtracesync; pf22, 21. ecb active low input signal sent by flash device to the eim whenever the flash device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence. lba active low signal sent by flash device causing external burst device to latch the starting burst address. bclk clock signal sent to external synchronous memories (such as burst flash) during burst mode. rw rw signal?indicates whether external access is a read (high) or write (low) cycle. this signal is also shared with the pcmcia pc_we . ras sdram/mddr row address select signal cas sdram/mddr column address select signal sdwe sdram write enable signal sdcke0 sdram clock enable 0
i.mx27 and i.mx27l data sheet, rev. 1.3 28 freescale semiconductor signal descriptions sdcke1 sdram clock enable 1 sdclk sdram clock sdclk_b sdram clock_b nfwe_b nfc write enable signal, multiplexed with etmpipestat2; pf6 nfre_b nfc read enable signal, multiplexed with etmpipestat1; pf5 nfale nfc address latch signal, multiplexed with etmpipestat0; pf4 nfcle nfc command latch signal, multiplexed with etmtracepkt0; pf1 nfwp_b nfc write permit signal, multiplexed with etmtracepkt1; pf2 nfce_b nfc chip enable signal, multiplexed with etmtracepkt2; pf3 nfrb nfc read busy signal, multiplexed with etmtracepkt3; pf0 d[15:0] data bus signal, shared with emi, pcmcia, and nfc pc_cd1_b pcmcia card detect signal, multiplexed with ata ata_dior signal; pf20 pc_cd2_b pcmcia card detect signal, multiplexed with ata ata_diow signal; pf19 pc_wait_b pcmcia wait signal, multiplexed with ata ata_cs1 signal; pf18 pc_ready pcmcia ready/irq signal, multiplexed with ata ata_cs0 signal; pf17 pc_pwron pcmcia signal, multiplexed with ata ata_da2 signal; pf16 pc_vs1 pcmcia voltage sense signal, multiplexed with ata ata_da1 signal; pf14 pc_vs2 pcmcia voltage sense signal, multiplexed with ata ata_da0 signal; pf13 pc_bvd1 pcmcia battery voltage detect signal, multiplexed with ata ata_dmarq signal; pf12 pc_bvd2 pcmcia battery voltage detect signal, multiplexed with ata ata_dmack signalpf11 pc_rst pcmcia card reset signal, multiplexed with ata ata_reset_b signal; pf10 iois16 pcmcia mode signal, multiplexed with ata ata_intrq signal; pf9 pc_rw_b pcmcia read write signal, multiplexed with ata ata_iordy signal; pf8 pc_poe pcmcia output enable signal, multiplexed with ata ata_buffer_en signal; pf7 clocks and resets clko clock out signal selected from internal clock signals. refer to the clock controller for internal clock selection; pf15. ext_60m this is a special factory test signal. to ensure proper operation, connect this signal to ground. ext_266m this is a special factory test signal. to ensure proper operation, connect this signal to ground. osc26m_test this is a special factory test signal. to ensure proper operation, leave this signal as a no connect. reset_in master reset?external active low schmitt trigger input signal. when this signal goes active, all modules (except the reset module, sdramc module, and the clock control module) are reset. table 3. i.mx27/mx27l signal descriptions (continued) pad name function/notes
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 29 signal descriptions reset_out reset_out?output from the internal hreset_b; and the hreset can be caused by all reset source: power on reset, system reset (reset_in), and watchdog reset. por power on reset?active low schmitt trigger input signal. the por signal is normally generated by an external rc circuit designed to detect a power-up event. xtal26m oscillator output to external crystal extal26m crystal input (26 mhz), or a 16 mhz to 32 mhz oscillator (or square-wave) input when internal oscillator circuit is shut down. clkmode[1:0] these are special factory test signals. to ensure proper operation, do not connect to these signals. extal32k 32 khz crystal input (note: in the rtc power domain) xtal32k oscillator output to 32 khz crystal (note: in the rtc power domain) power_cut (note: in the rtc power domain) power_on_reset (note: in the rtc power domain) osc32k_bypass the signal for osc32k input bypass (note: in the rtc power domain) bootstrap boot [3:0] system boot mode select?the operational system boot mode of the i.mx27/mx27l processor upon system reset is determined by the settings of these pins. boot[1:0] are also used as handshake signals to pmic(vstby). jtag jtag_ctrl jtag controller select signal?jtag_ctrl is sampled during rising edge of trst. must be pulled to logic high for proper jtag interface to debugger. pulling jtag_crtl low is for internal test purposes only. trst test reset pin?external active low signal used to asynchronously initialize the jtag controller. tdo serial output for test instructions and data. changes on the falling edge of tck. tdi serial input for test instructions and data. sampled on the rising edge of tck. tck test clock to synchronize test logic and control register access through the jtag port. tms test mode select to sequence jtag test controller?s state machine. sampled on rising edge of tck. rtck jtag return clock used to enhance stability of jtag debug interface devices. this signal is multiplexed with 1-wire; thus, utilizing 1-wire will render rtck unusable and vice versa; pe16. secure digital interface (x2) sd1_cmd sd command bidirectional signal?if the system designer does not want to make use of the internal pull-up, via the pull-up enable register, a 4. 7k?69 k external pull up resistor must be added. this signal is multiplexed with cspi3_mosi; pe22. sd1_clk sd output clock. this signal is multiplexed with cspi3_sclk; pe23. table 3. i.mx27/mx27l signal descriptions (continued) pad name function/notes
i.mx27 and i.mx27l data sheet, rev. 1.3 30 freescale semiconductor signal descriptions sd1_d[3:0] sd data bidirectional signals?if the system designer does not want to make use of the internal pull-up, via the pull-up enable register, a 50 k?69 k external pull up resistor must be added. sd1_d[3] is muxed with cspi3_ss while sd1_d[0] is muxed with cspi3_miso pe21?18. sd2_cmd sd command bidirectional signal. this signal is multiplexed with mshc_bs; through gpio multiplexed with slcdc1_cs; pb8. sd2_clk sd output clock signal. this signal is multiplexed with mshc_sclk, through gpio multiplexed with slcdc1_clk; pb9. sd2_d[3:0] sd data bidirectional signals. sd2_d[3:0] multiplexed with mshc_data[0:3], also through gpio sd2_1:0] multiplexed with slcdc1_rs and sldcd1_d0; pb7?pb4. sd3_cmd sd command bidirectional signal. this signal is multiplexed with etmtracepkt15 and also through gpio pd1 multiplexed with fec_txd0. sd3_clk sd output clock signal. this signal is through gpio pd0 multiplexed with fec_txd1. note: sd3_data is multiplexed with ata_data3?0. uarts (x6) uart1_rts request to send input signal; pe15 uart1_cts clear to send output signal; pe14 uart1_rxd receive data input signal; pe13 uart1_txd transmit data output signal, pe12 uart2_rxd receive data input signal. this signal is multiplexed with kp_row6 signal from kpp; pe7. uart2_txd transmit data output signal. this signal is multiplexed with kp_col6 signal from kpp; pe6. uart2_rts request to send input signal. this signal is multiplexed with kp_row7 signal from kpp; pe4. uart2_cts clear to send output signal. this signal is multiplexed with kp_col7 signal from kpp; pe3. uart3_rts request to send input signal, pe11 uart3_cts clear to send output signal; pe10 uart3_rxd receive data input signal; pe9 uart3_txd transmit data output signal; pe8 note: uart 4, 5, and 6 are multiplexed with coms sensor interface signals. keypad kp_col[5:0] keypad column selection signals. kp_col[7:6] are multiplexed with uart2_cts and uart2_txd respectively. alternatively, kp_col6 is also available on the internal factory test signal test_wb2. the function multiplexing control register in the system control chapter must be used in conjunction with programming the gpio multiplexing (to select the alternate signal multiplexing) to choose which signal kp_col6 is available. kp_row[5:0] keypad row selection signals. kp_row[7:6] are multiplexed with uart2_rts and uart2_rxd signals respectively. the function multiplexing control register in the system control chapter must be used in conjunction with programming the gpio multiplexing (to select the alternate signal multiplexing) to choose which signals kp_row6 and kp_row7 are available. table 3. i.mx27/mx27l signal descriptions (continued) pad name function/notes
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 31 signal descriptions note: kp_col[7:6] and kp_row[7:6] are multiplexed with uart2 signals as show above, also see uarts table. pwm pwmo pwm output. this signal is multiplexed with pc_spkout of pcmcia, as well as tout2 and tout3 of the general purpose timer module; pe5. cspi (x3) cspi1_mosi master out/slave in signal, pd31 cspi1_miso master in/slave out signal, pd30 cspi1_ss[2:0] slave select (selectable polarity) signal, the cspi1_ss2 is multiplexed with usbh2_data5/rcv; and cspi1_ss1 is multiplexed with ext_dmagrant ; pd26?28. cspi1_sclk serial clock signal, pd29 cspi1_rdy serial data ready signal, shared with ext_dmareq_b signal; pd25 cspi2_mosi master out/slave in signal, multiplexed with usbh2_data1/txdp; pd24 cspi2_miso master in/slave out signal, multiplexed with usbh2_data2/txdm; pd23 cspi2_ss[2:0] slave select (selectable polarity) signals, multiplexed with usbh2_data4/rxdm, usbh2_data3/rxdp, usbh2_data6/speed; pd19?pd21 cspi2_sclk serial clock signal, multiplexed with usbh2_data0/oen; pd22 note: cspi3 cspi3_mosi, cspi3_miso, cspi3_ss, andcspi3_sclk are multiplexed with sd1 signals. i 2 c i2c2_scl i 2 c2 clock, through gpio, multiplexed with slcdc_data8; pc6 i2c2_sda i 2 c2 data, through gpio, multiplexed with slcdc_data7; pc5 i2c_clk i 2 c1 clock; pd18 i2c_data i 2 c1 data; pd17 cmos sensor interface csi_hsync sensor port horizontal sync, multiplexed with uart5_rtsp; pb21 csi_vsync sensor port vertical sync, multiplexed with uart5_cts; pb20 csi_d7 sensor port data, multiplexed with uart5_rxd; pb19 csi_d6 sensor port data, multiplexed with uart5_txd; pb18 csi_d5 sensor port data; pb17 csi_pixclk sensor port data latch clock; pb16 csi_mclk sensor port master clock, pb15 csi_d4 sensor port data, pd14 csi_d3 sensor port data, multiplexed with uart6_rts; pb13 csi_d2 sensor port data, multiplexed with uart6_cts; pb12 table 3. i.mx27/mx27l signal descriptions (continued) pad name function/notes
i.mx27 and i.mx27l data sheet, rev. 1.3 32 freescale semiconductor signal descriptions csi_d1 sensor port data, multiplexed with uart6_rxd; pb11 csi_d0 sensor port data, multiplexed with uart6_txd; pb10 serial audio port?ssi (configurable to i2s protocol and ac97) (2 to 4) ssi1_clk serial clock signal that is output in master or input in slave; pc23 ssi1_txd transmit serial data; pc22 ssi1_rxd receive serial data; pc21 ssi1_fs frame sync signal that is output in master and input in slave; pc20 ssi2_clk serial clock signal that is output in master or input in slave, multiplexed with gpt4_tin. pc27 ssi2_txd transmit serial data signal, multiplexed with gpt4_tout; pc26 ssi2_rxd receive serial data, multiplexed with gpt5_tin; pc25 ssi2_fs frame sync signal which is output in master and input in slave, multiplexed with gpt5_tout: pc24 ssi3_clk serial clock signal which is output in master or input in slave. this signal is multiplexed with slcdc2_clk; through gpio multiplexed with pc_wait_b; pc31. ssi3_txd transmit serial data signal which is multiplexed with slcdc2_cs, through gpio multiplexed with pc_ready; pc30 ssi3_rxd receive serial data which is multiplexed with slcdc2_rs; through gpio multiplexed with pc_vs1; pc29 ssi3_fs frame sync signal which is output in master and input in slave. this signal is multiplexed with slcdc2_d0; through gpio multiplexed with pc_vs1; pc28. ssi4_clk serial clock signal which is output in master or input in slave; through gpio multiplexed with pc_bvd1; pc19 ssi4_txd transmit serial data; through gpio multiplexed with pc_bvd2; pc18 ssi4_rxd receive serial data; through gpio multiplexed with iois16; pc17 ssi4_fs frame sync signal which is output in master and input in slave; pc16 general purpose timers (x6) tin timer input capture or timer input clock?the signal on this input is applied to gpt 1?3 simultaneously. this signal is muxed with the walk-up guard mode wkgd signal in the pll, clock, and reset controller module, and is also multiplexed with gpt6_tout; pc15. tout1 timer output signal from general purpose timer1 (gpt1). this signal is multiplexed with ssi1_mclk and ssi2_mclk signal of ssi1 and ssi2. the pin name of this signal is simply tout, and is also multiplexed with gpt6_tin; pc14. note: tout2, tout3 are multiplexed with pwmo pad; gpt4 and gpt5 signals are multiplexed with ssi2 pads. usb2.0 usbotg_dir/txdm usb otg direction/transmit data minus signal, multiplexed with kp_row7a; pe2 usbotg_stp/txdm usb otg stop signal/transmit data minus signal, multiplexed with kp_row6a; pe1 table 3. i.mx27/mx27l signal descriptions (continued) pad name function/notes
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 33 signal descriptions usbotg_nxt/txdm usb otg next/transmit data minus signal, multiplexed with kp_col6a; pe0 usbotg_clk/txdm usb otg clock/transmit data minus signal, pe24 usbotg_data7/suspend usb otg data7/suspend signal, pe25 usbh2_stp/txdm usb host2 stop signal/transmit data minus signal, pa4 usbh2_nxt/txdm usb host2 next/transmit data minus signal, pa3 usbh2_data7/suspend usb host2 data7/suspend signal, pa2 usbh2_dir/txdm usb host2 direction/transmit data minus signal, pa1 usbh2_clk/txdm usb host2 clock/transmit data minus signal; pa0 usbotg_data3/rxdp usb otg data4/receive data plus signal; multiplexed with slcdc1_dat15 through pc13 usbotg_data4/rxdm usb otg data4/receive data minus signal; multiplexed with slcdc1_dat14 through pc12 usbotg_data1/txdp usb otg data1/transmit data plus signal; multiplexed with slcdc1_dat13 through pc11 usbotg_data2/txdm usb otg data2/transmit data minus signal; multiplexed with slcdc1_dat12 through pc10 usbotg_data0/oen usb otg data0/output enable signal; multiplexed with slcdc1_dat11 through pc9 usbotg_data6/speed usb otg data6/suspend signal; multiplexed with slcdc1_dat10 and usbg_txr_int_b through pc8 usbotg_data5/rcv usb otg data5/rcv signal; multiplexed with slcdc1_dat9 through pc7 usbh1_rxdp usb host1 receive data plus signal, multiplexed with uart4_rxd; multiplexed with slcdc1_dat6 and uart4_rts_alt through pb31 usbh1_rxdm usb host1 receive data minus signal; multiplexed with slcdc1_dat5 and uart4_cts through pb30 usbh1_txdp usb host1 transmit data plus signal; multiplexed with uart4_cts, multiplexed with slcdc1_dat4 and uart4_rxd_alt through pb29 usbh1_txdm usb host1 transmit data minus signal; multiplexed with uart4_txd, multiplexed with slcdc1_dat3 through pb28 usbh1_oe_b usb host1 output enable signal; multiplexed with slcdc1_dat2 through pb27 usbh1_fs usb host1 full speed output signal, multiplexed with uart4_rts, multiplexed with slcdc1_dat1 through pb26 usbh1_rcv usb host1 rcv signal; multiplexed with slcdc1_dat0 through pb25 usb_oc_b usb oc signal. pb24 usb_pwr usb power signal; pb23 usbh1_susp usb host1 suspend signal; pb22 lcd controller and smart lcd controller oe_acd alternate crystal direction/output enable; pa31 contrast this signal is used to control the lcd bias voltage as contrast control; pa30 table 3. i.mx27/mx27l signal descriptions (continued) pad name function/notes
i.mx27 and i.mx27l data sheet, rev. 1.3 34 freescale semiconductor signal descriptions vsync frame sync or vsync?this signal also serves as the clock signal output for gate; driver (dedicated signal sps for sharp panel hr-tft); pa29. hsync line pulse or hsync; pa28 spl_spr sampling start signal for left and right scanning. through gpio, this signal is multiplexed with the slcdc1_clk; pa27. ps control signal output for source driver (sharp panel dedicated signal). this signal is multiplexed with the slcdc1_cs; pa26. cls start signal output for gate driver. this signal is invert version of ps (sharp panel dedicated signal). this signal is multiplexed with the slcdc1_rs; pa25. rev signal for common electrode driving signal preparation (sharp panel dedicated signal). this signal is multiplexed with slcdc1_d0; pa24. ld [17:0] lcd data bus?all lcd signals are driven low after reset and when lcd is off. through gpio, ld[15:0] signals are multiplexed with slcdc1_dat[15:0], slcdc. pa23?pa6. lsclk shift clock; pa5 note: slcdc signals are multiplexed with lcdc signals. ata (not available on i.mx27l) ata_data15?0 ata data bus, [15:0] are multiplexed with etmtracepkt4?12, fec_mdio, etmtracepkt13?14 sd3_d3?0; through gpio also are multiplexed with slcdc 15?0, and fec signals; pf23, pd16?pd2. noisy i/o supply pins n vdd 1?15, a vdd noisy supply for the i/o pins. there are 16 i/o voltage pads, n vdd 1 through n vdd 15 + a vdd . analog supply pins fpm vdd mpll vdd osc26 vdd upll vdd osc32 vdd osc32vss supply for analog blocks fpmvss mpllvss osc26vss upllvss quiet gnd for analog blocks q vdd internal power supply q vdd power supply pins for silicon internal circuitry qvss gnd pins for silicon internal circuitry table 3. i.mx27/mx27l signal descriptions (continued) pad name function/notes
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 35 signal descriptions 3.1 power-up sequence the i.mx27/mx27l processor consists of three major sets for power supply voltage named q vdd (core logic supply), fuse vdd (analog supply for fusebox), and n vdd vdda (io supply). the external voltage regulators and power-on devices must provide the applications processor with a specific sequence of power and resets to ensure proper operation. it is important that the applications processor power supplies be powered-up in a certain order to avoid unintentional fuse blown. q vdd should be powered up before fuse vdd . the recommended order is: 1. q vdd (1.5 v) 2. fuse vdd (1.8 v) n vdd (1.8/2.775 v), and analog supplies (2.775 v). see table 3 for signal descriptions. or 1. q vdd (1.5 v), n vdd (1.8/2.775 v), and analog supplies (2.775 v). see table 3 for signal descriptions. 2. fuse vdd (1.8 v). fuse vdd for fuse vdd rtc vdd for rtc, scc power supply rtcvss for rtc, scc gnd note: both 1-wire and fast ethernet controller signals are multiplexed with other signals. as a result these signal names do not appear in this list. the signals are listed below with the named signal that they are multiplexed. 1-wire signals: the 1-wire input and output signal is multiplexed with jtag rtck pad, pe16. fast ethernet controller (fec) signals on the i.mx27. the ata module does not exist on the i.mx27l: fec_tx_en: transmit enable signal, through gpio multiplexed with ata_data15 pad; pf23 fec_tx_er: transmit data error; through gpio multiplexed with ata_data14 pad; pd16 fec_col: collision signal; through gpio multiplexed with ata_data13 pad; pd15 fec_rx_clk: receive clock signal; through gpio multiplexed with ata_data12 pad; pd14 fec_rx_dv: receive data valid signal; through gpio multiplexed with ata_data11 pad; pd13 fec_rxd0: receive data0; through gpio multiplexed with ata_data10 pad; pd12 fec_tx_clk: transmit clock signal; through gpio multiplexed with ata_data9 pad; pd11 fec_crs: carrier sense enable; through gpio multiplexed with ata_data8 pad; pd10 fec_mdc: management data clock; through gpio multiplexed with ata_data7 pad; pd9 fec_mdio: management data input/output, multiplexed with ata_data6 pad; pd8 fec_rxd3?1: receive data; through gpio multiplexed with ata_data5?3 pad; pd7?5 fec_rx_er: receive data error; through gpio multiplexed with ata_data2 pad; pd4 fec_txd3?2: transmit data; through gpio multiplexed with ata_data1?0; pad; pd3?2 fec_txd1: transmit data; through gpio multiplexed with sd3_clk pad; pd1 fec_txd0: transmit data; through gpio multiplexed with sd3_cmd pad; pd0 note: the rest ata signals are multiplexed with pcmcia pads. table 3. i.mx27/mx27l signal descriptions (continued) pad name function/notes
i.mx27 and i.mx27l data sheet, rev. 1.3 36 freescale semiconductor signal descriptions 3.2 emi pins multiplexing this section discusses the multiplexing of emi signa ls. the emi signals? multiplexing is done inside the emi. table 4 lists the i.mx27 pin names, pad types, a nd the memory devices? equivalent pin names. table 4. emi multiplexing pin name pad type weim sdram pcmcia ddr nfc a0 regular a0 ma0 a0 ma0 ? a1 regular a1 ma1 a1 ma1 ? a2 regular a2 ma2 a2 ma2 ? a3 regular a3 ma3 a3 ma3 ? a4 regular a4 ma4 a4 ma4 ? a5 regular a5 ma5 a5 ma5 ? a6 regular a6 ma6 a6 ma6 ? a7 regular a7 ma7 a7 ma7 ? a8 regular a8 ma8 a8 ma8 ? a9 regular a9 ma9 a9 ma9 ? a10 regular a10 ? a10 ? ? ma10 regular ? ma10 ? ma10 ? a11 regular a11 ma11 a11 ma11 ? a12 regular a12 ma12 a12 ma12 ? a13 regular a13 ma13 a13 ma13 ? a14 regular a14 ? a14 ? ? a15 regular a15 ? a15 ? ? a16 regular a16 ? a16 ? ? a17 regular a17 ? a17 ? ? a18 regular a18 ? a18 ? ? a19 regular a19 ? a19 ? ? a20 regular a20 ? a20 ? ? a21 regular a21 ? a21 ? ? a22 regular a22 ? a22 ? ? a23 regular a23 ? a23 ? ? a24 regular a24 ? a24 ? ? a25 regular a25 ? a25 ? ? sdba1 regular ? sdba1 ce1 ?? sdba0 regular ? sdba0 ce2 ?? sd0ddr?sd0??? sd1ddr?sd1???
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 37 signal descriptions sd2ddr?sd2??? sd3ddr?sd3??? sd4ddr?sd4??? sd5ddr?sd5??? sd6ddr?sd6??? sd7ddr?sd7??? sd8ddr?sd8??? sd9ddr?sd9??? sd10 ddr ? sd10 ? ? ? sd11 ddr ? sd11 ? ? ? sd12 ddr ? sd12 ? ? ? sd13 ddr ? sd13 ? ? ? sd14 ddr ? sd14 ? ? ? sd15 ddr ? sd15 ? ? ? sd16 ddr ? sd16 ? ? ? sd17 ddr ? sd17 ? ? ? sd18 ddr ? sd18 ? ? ? sd19 ddr ? sd19 ? ? ? sd20 ddr ? sd20 ? ? ? sd21 ddr ? sd21 ? ? ? sd22 ddr ? sd22 ? ? ? sd23 ddr ? sd23 ? ? ? sd24 ddr ? sd24 ? ? ? sd25 ddr ? sd25 ? ? ? sd26 ddr ? sd26 ? ? ? sd27 ddr ? sd27 ? ? ? sd28 ddr ? sd28 ? ? ? sd29 ddr ? sd29 ? ? ? sd30 ddr ? sd30 ? ? ? sd31 ddr ? sd31 ? ? ? dqm0 ddr ? dqm0 ? ? ? dqm1 ddr ? dqm1 ? ? ? dqm2 ddr ? dqm2 ? ? ? dqm3 ddr ? dqm3 ? ? ? eb0 regular eb0 ? reg ? ? table 4. emi multiplexing (continued) pin name pad type weim sdram pcmcia ddr nfc
i.mx27 and i.mx27l data sheet, rev. 1.3 38 freescale semiconductor signal descriptions eb1 regular eb1 ? iord ? ? oe regular oe ? iowr ? ? cs0regularcs0???? cs1regularcs1???? cs2 regular cs2 csd0 ? ? ? cs3 regular cs3 csd1 ? ? ? cs4regularcs4???? cs5regularcs5???? ecbregularecb???? lba regular lba ? oe ?? bclkregularbclk???? rw regular rw ? we ? ? ras regular ? ras ? ? ? cas regular ? cas ? ? ? sdwe regular ? sdwe ? ? ? sdcke0 regular ? sdcke0 ? ? ? sdcke1 regular ? sdcke1 ? ? ? sdclk regular ? sdclk ? ? ? sdclk ?????? sdqs0 ddr ? ? ? sdqs0 ? sdqs1 ddr ? ? ? sdqs1 ? sdqs2 ddr ? ? ? sdqs2 ? sdqs3 ddr ? ? ? sdqs3 ? nfwe regular????we nfre regular????re nfaleregular????ale nfcleregular????cle nfwp regular????wp nfce regular????ce nfrbregular????r/b d15 regular d15 ? d15 ? d15 d14 regular d14 ? d14 ? d14 d13 regular d13 ? d13 ? d13 d12 regular d12 ? d12 ? d12 d11 regular d11 ? d11 ? d11 table 4. emi multiplexing (continued) pin name pad type weim sdram pcmcia ddr nfc
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 39 signal descriptions d10 regular d10 ? d10 ? d10 d9 regular d9 ? d9 ? d9 d8 regular d8 ? d8 ? d8 d7 regular d7 ? d7 ? d7 d6 regular d6 ? d6 ? d6 d5 regular d5 ? d5 ? d5 d4 regular d4 ? d4 ? d4 d3 regular d3 ? d3 ? d3 d2 regular d2 ? d2 ? d2 d1 regular d1 ? d1 ? d1 d0 regular d0 ? d0 ? d0 pc_cd1 regular ? ? cd1 ?? pc_cd2 regular ? ? cd2 ?? pc_wait regular ? ? wait ?? pc_ready regular ? ? ready ? ? pc_pwron regular ? ? pc_pwron ? ? pc_vs1 regular ? ? vs1 ? ? pc_vs2 regular ? ? vs2 ? ? pc_bvd1 regular ? ? bvd1 ? ? pc_bvd2 regular ? ? bvd2 ? ? pc_rst regular ? ? rst ? ? iois16 regular ? ? iois16/wp ? ? pc_rw regular ? ? rw ?? pc_poe regular ? ? poe ? ? m_requestregular????? m_grantregular????? table 4. emi multiplexing (continued) pin name pad type weim sdram pcmcia ddr nfc
i.mx27 and i.mx27l data sheet, rev. 1.3 40 freescale semiconductor electrical characteristics 4 electrical characteristics this section provides the chip-level and module-leve l electrical characteristics for the i.mx27/imx27l. 4.1 i.mx27/imx27l chip-level conditions this section provides the chip-level electrical characteristics for the ic. see table 5 for a quick reference to the individual tables and sections. table 6 provides the dc absolute maximum operating conditions. caution stresses beyond those listed under table 6 may cause permanent damage to device. these are stress ratings only. functional operation of device at these or any other conditions beyond those indicated under ?dc operating conditions? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. table 7 provides the dc recommended operating conditions. table 5. i.mx27/imx27l chip-level conditions for these characteristics? topic appears? table 6, ?dc absolute maximum conditions? on page 40 table 7, ?dc operating conditions? on page 40 table 9, ?interface frequency? on page 41 table 10, ?frequency definition for power consumption measurement? on page 42 table 11, ?current consumption? on page 42 section 4.1.3, ?test conditions and recommended settings? on page 43 table 6. dc absolute maximum conditions ref. num parameter symbol min max units 1 supply voltage v ddmax ?0.5 1.52 v 2 supply voltage (level shift i/o) v ddiomax ?0.5 3.3 v 3 input voltage range v imax ?0.5 nv dd (1, 5?13) + 0.3 v 4 storage temperature range t storage ?20 125 o c table 7. dc operating conditions id parameter symbol min typical max units 1 core supply voltage (@266 mhz) qv dd 1.2 1.3 1.52 v 2 core supply voltage (@400 mhz) qv dd 1.38 1.45 1.52 v
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 41 electrical characteristics 4.1.1 dpll frequency specification table 8 provides the frequency specifications for the dpll. table 9 provides information for interface frequency limits. 3 rtc, scc separate supply voltage rtc vdd 1.2 ? 1.52 v 4 i/o supply voltage, fast (7, 11, 12, 14, 15) 1 nv dd_fast 1.75 ? 2.8 v 5 i/o supply voltage, slow (5, 6, 8, 9, 10, 13, av dd )nv dd_slow 1.75 ? 3.05 v nv dd_slow 1.75 ? 3.1 v 6 i/o supply voltage, ddr (1, 2, 3, 4) 2 nv dd_ddr 1.75 ? 1.9 v 7 analog supply voltage: fpmv dd , upllv dd , mpllv dd v dd 1.35 1.4 1.6 v 8 fusebox read supply voltage fusev dd (read mode) 1.7 1.875 1.95 v 9 fusebox program supply voltage fusev dd (program mode) 3.00 3.15 3.30 v 10 osc32v dd v osc32 1.1 ? 1.6 v 11 osc26v dd v osc26 2.68 ? 2.875 v 12 operating ambient temperature (17mm x17mm package) t a ?20 ? 85 o c 13 operating ambient temperature (19mm x19mm package) t a ?40 ? 85 o c note: 1 segments 11, 14, 15 are mixture of fast and slow gpio. 2 segments 1, 3, 4 are mixture of ddr and fast gpio. table 8. dpll frequency specifications parameter min typical max unit output duty cycle (dpdck) 48.5 50.0 51.5 % output duty cycle (dpgdck_2) 48.5 50.0 51.5 % frequency lock time (fol mode or non-integer mf) ??80s phase lock time ? ? 100 s cycle-to-cycle jitter ? ? 0.2 ns table 9. interface frequency id parameter symbol min typical max units 1 jtag: tck frequency of operation f jtag dc 5 33.25 mhz table 7. dc operating conditions (continued) id parameter symbol min typical max units
i.mx27 and i.mx27l data sheet, rev. 1.3 42 freescale semiconductor electrical characteristics 4.1.2 current consumption table 10 defines the frequency settings used for specifying power consumption in table 11 . all power states are specified. the temperature setting of 25 c is used for specifying the deep sleep mode (dsm) per the temperature range shown in table 7 . table 11 shows the power consumption for the i.mx27/imx27l device. table 10. frequency definition for power consumption measurement id parameter symbol value units 1 mcu core f mcumeas@266 266 mhz 2 mcu core f mcumeas@400 400 mhz 3 mcu ahb bus f mcu-ahbmeas 133 mhz 4 mcu ip bus f mcu-ipmeas 66 mhz 5osc32 f osc32khzmeas 32.768 khz table 11. current consumption id parameter conditions symbol typical units 1 run current (qv dd current) run current at 266 mhz qv dd = 1.3 v idd run 260 ma run current at 400 mhz qv dd = 1.45 v idd run 300 ma 2 doze current ? qv dd = 1.2 v ?nv dd = 1.75 v ? arm is in wait for interrupt mode. ? arm well bias is enabled. ? mcu pll is on. ? spll is off. ? fpm is on. ? 26mhz oscillator is on. ? 32 khz oscillator is on. ? other modules are off. ?t a = 25 c. idd doze 11 ma 3 sleep current ? qv dd = 1.2 v. ?nv dd = 1.75 v. ? both plls are off. ? fpm is off. ? arm well bias is enabled. ? 32 khz oscillator is on. ? 26mhz oscillator is off. ? all the modules are off. ?t a = 25 c. idd sleep 900 a 4 power gate ? nv dd13 is on. see ta b l e 7 for specific values. ?rtc vdd , osc32 vdd are on. see ta b l e 7 for specific values. ? all other v dd = 0 v ?t a = 25 c. idd pg 75 a
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 43 electrical characteristics 4.1.3 test conditions and recommended settings unless specified, ac timing parameters are specified for 15 pf loading on i.mx27/imx27l pads. drive strength has been kept at default/reset values for testing. emi timing has been verified with high drive strength setting and 25 pf loads. sdhc timing has also been verified with high drive strength setting. unless otherwise noted, ac/dc parameters ar e guaranteed at operating conditions shown in table 7 . 4.2 module-level electrical specifications this section contains the i.mx27/imx27l electrical information including timing specifications, arranged in alphabetical order by module name. 4.2.1 pads io (padio) electricals 4.2.1.1 dc electrical characteristics the over-operating characteristics appear in table 12 for gpio pads and table 13 for ddr (double data rate) pads (unless otherwise noted). table 12. gpio pads dc electrical parameters parameter symbol test conditions min typical max units high-level output voltage v oh i oh = -1 ma n vdd -0.15 ? ? v i oh = specified drive 0.8*n vdd ??v low-level output voltage v ol i ol = 1 ma ? ? 0.15 v i ol = specified drive ? ? 0.2*n vdd v high-level output current, slow slew rate i oh_s v oh = 0.8*n vdd normal high max high 1 ?2 ?4 ?8 ??ma high-level output current, fast slew rate i oh_f v oh = 0.8*n vdd normal high max high 1 ?4 ?6 ?8 ??ma low-level output current, slow slew rate i ol_s v ol = 0.2*n vdd normal high max high 1 2 4 8 ??ma low-level output current, fast slew rate i ol_f v ol = 0.2*n vdd normal high max high 1 4 6 8 ??ma input hysteresis v hys hysteresis enabled 0.25 ? ? v schmitt trigger vt+ v t + hysteresis enabled 0.5*q vdd ??v schmitt trigger vt- v t - hysteresis enabled ? ? 0.5*q vdd v
i.mx27 and i.mx27l data sheet, rev. 1.3 44 freescale semiconductor electrical characteristics pull-up resistor (22 k pu) r pu ?152259 k pull-up resistor (47 k pu) r pu ? 30 47 128 pull-up resistor (100 k pu) r pu ? 34 100 268 pull-down resistor (100 k pd) r pd ? 25 100 343 input current (no pu/pd) i in v i = 0 v i = n vdd ?0.33 1 a input current (22 k pu) i in v i = 0 v i = n vdd ? ? 115 0.1 a a input current (47 k pu) i in v i = 0 v i = n vdd ??53 0.1 a a input current (100 k pu) i in v i = 0 v i = n vdd ??25 0.1 a a input current (100 k pd) i in v i = 0 v i = n vdd ? ? 0.25 28 a a tri-state input leakage current i z v i = n vdd or 0 i/o = high z ?0.33 2 a high level dc input voltage v ih ? 0.7*v ddio ?v ddio v low-level dc input voltage v il ? 0 ? 0.3*v ddio v note: 1 max high strength should be avoided due to excessive overshoot and ringing. table 13. ddr (double data rate) i/ o pads dc electrical parameters parameter symbol test conditions min typical max units high-level output voltage v oh i oh = -1 ma nv dd_ddr ?0.08 ??v i oh = specified drive 0.8*nv dd_ ddr ??v low-level output voltage v ol i ol = 1 ma ? ? 0.08 v i ol = specified drive ? ? 0.2*nv dd_ ddr v high-level output current i oh v oh =0.8*nv dd_ddr normal high max high 1 ddr drive 1 ?3.6 ?7.2 ?10.8 ?14.4 ??ma table 12. gpio pads dc electrical parameters (continued) parameter symbol test conditions min typical max units
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 45 electrical characteristics 4.2.1.2 ac electrical characteristics figure 2 depicts the load circuit for output pads. figure 3 depicts the output pad transition time waveform. the range of operating conditions appear in table 14 for slow general i/o, table 15 for fast general i/o, and table 16 for ddr i/o (unless otherwise noted). figure 2. load circuit for output pad figure 3. output pad transition time waveform low-level output current i ol v ol =0.2*nv dd_ddr normal high max high 1 ddr drive 1 3.6 7.2 10.8 14.4 ??ma low-level input current i il v i = 0 ? 1.7 2 a high-level input current i ih v i = nv dd_ddr ?2 a tri-state current i z v i = nv dd_ddr or 0 i/o = high z ?1.7 2 a note: 1 max high and ddr drive strengths should be avoided due to excessive overshoot and ringing. table 14. ac electrical characteristics of slow general i/o pads id parameter symbol test condition min typical max units pa1 output pad transition times (max high) tpr 25 pf 50 pf 1.25 1.95 1.9 2.9 3.2 4.75 ns output pad transition times (high) tpr 25 pf 50 pf 1.45 2.6 ?4.8 8.4 ns output pad transition times (standard drive) tpr 25 pf 50 pf 2.6 5.1 ?8.5 16.5 ns ? maximum input transition times 1 trm ? ? ? 25 ns note: table 13. ddr (double data rate) i/o pads dc electrical parameters (continued) parameter symbol test conditions min typical max units te s t po i n t from output under test cl cl includes package, probe and jig capacitance 0 v nvdd 20% 80% 80% 20% pa 1 pa 1 output (at pad)
i.mx27 and i.mx27l data sheet, rev. 1.3 46 freescale semiconductor electrical characteristics 4.2.2 1-wire electrical specifications figure 4 depicts the rpp timing, and table 17 lists the rpp timing parameters. figure 4. reset and presence pulses (rpp) timing diagram 1 hysteresis mode is recommended for input with transition time greater than 25 ns. table 15. ac electrical characteristics of fast general i/o pads id parameter symbol test condition min typical max units pa1 output pad transition times (max high) tpr 25 pf 50 pf 0.9 1.7 1.2 2.4 2.0 4.0 ns output pad transition times (high) tpr 25 pf 50 pf 1.15 2.3 1.6 3.1 2.7 5.3 ns output pad transition times (normal) tpr 25 pf 50 pf 1.7 3.4 2.4 4.7 4.0 8.0 ns ? maximum input transition times 1 1 hysteresis mode is recommended for input with transition time greater than 25 ns. trm ? ? ? 25 ns note: table 16. ac electrical characteristics of ddr i/o pads id parameter symbol test condition min typical max units pa1 output pad transition times (ddr drive) tpr 25 pf 50 pf 0.5 1.0 0.75 1.45 1.2 2.4 ns output pad transition times (max high) tpr 25 pf 50 pf 0.67 1.3 1.0 2.0 1.6 3.1 ns output pad transition times (high) tpr 25 pf 35 pf 1.0 1.95 1.5 2.9 2.4 4.7 ns output pad transition times (normal) tpr 25 pf 50 pf 2.0 3.9 2.9 5.9 4.8 8.4 ns ? maximum input transition times trm ? ? ? 5 ns one-wire bus ds2502 tx ?presence pulse? (batt_line) 1-wire tx ?reset pulse? ow1 ow2 ow3 ow4
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 47 electrical characteristics figure 5 depicts write 0 sequence timing, and table 18 lists the timing parameters. figure 5. write 0 sequence timing diagram figure 6 depicts write 1 sequence timing, figure 7 depicts the read sequence timing, and table 19 lists the timing parameters. figure 6. write 1 sequence timing diagram figure 7. read sequence timing diagram table 17. rpp sequence delay comparisons timing parameters id parameters symbol min typical max units ow1 reset time low t rstl 480 511 s ow2 presence detect high t pdh 15 ? 60 s ow3 presence detect low t pdl 60 ? 240 s ow4 reset time high t rsth 480 512 ? ? table 18. wr0 sequence timing parameters id parameter symbol min typical max units ow5 write 0 low time t wr0_low 60 100 120 s ow6 transmission time slot t slot ow5 117 120 s ow5 ow6 one-wire bus (batt_line) ow7 ow8 one-wire bus (batt_line) ow7 ow8 ow9 one-wire bus (batt_line)
i.mx27 and i.mx27l data sheet, rev. 1.3 48 freescale semiconductor electrical characteristics 4.2.3 ata electrical specifications this section describes the electrical information of the parallel ata module compliant with ata/atapi-6 specification. note the parallel ata module is not available on the i.mx27l parallel ata module can work on pio/multi-word dma/ultra dma transfer modes. each transfer mode has different data transfer rate, ultra dma mode 4 data transfer rate is up to 100 mb/s. parallel ata module interface consist of a total of 29 pins, some pins act on different function in different transfer mode. there are different requirements of timing relationships among the function pins conform with ata/atapi-6 specification and these requirements are configurable by the ata module registers. below defines the ac characteristics of all the interface signals on all data transfer modes. 4.2.3.1 general timing requirements these are the general timing requirements for the ata interface signals. table 19. write 1/read timing parameters id parameter symbol min typical max units ow7 write 1/read low time t low1 1515s ow8 transmission time slot t slot 60 117 120 s ow9 release time t release 15 ? 45 s table 20. ac characteristics of all interface signals id parameter symbol min max unit si1 rising edge slew rate for any signal on ata interface (see note) s rise ? 1.25 v/ns si2 falling edge slew rate for any signal on ata interface (see note) s fall ? 1.25 v/ns si3 host interface signal capacitance at the host connector c host ?20pf note: srise and sfall meets this requirement when measured at the sender?s connector from 10?90% of full signal amplitude with all capacitive loads from 15 pf through 40 pf where all signals have the same capacitive load value.
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 49 electrical characteristics figure 8. ata interface signals timing diagram 4.2.4 digital audio mux (audmux) the audmux provides a programmable interconnect logi c for voice, audio and data routing between internal serial interfaces (ssi, sap) and external se rial interfaces (audio and voice codecs). the ac timing of audmux external pins is hence governed by ssi and sap modules. please refer to their respective electrical specifications. 4.2.5 cmos sensor interface (csi) this section describes the electrical information (ac timing) of the csi. 4.2.5.1 gated clock mode timing vsync, hsync, and pixclk signals ar e used in this mode. a frame starts with a rising/falling edge on vsync, then hsync goes high and holds for the entire line. the pixel clock is valid as long as hsync is high. figure 9 and figure 10 depict the gated clock mode timings of csi, and table 21 lists the timing parameters. ata interface signals si1 si2
i.mx27 and i.mx27l data sheet, rev. 1.3 50 freescale semiconductor electrical characteristics figure 9 shows sensor output data on the pixel clock falli ng edge. the csi latches data on the pixel clock rising edge. figure 9. csi timing diagram, gated, pixclk?sensor data at falling edge, latch data at rising edge figure 10 shows sensor output data on the pixel clock risi ng edge. the csi latches data on the pixel clock falling edge. figure 10. csi timing diagram, gated, pixclk?sensor data at rising edge, latch data at falling edge vsync hsync pixclk data[7:0] va li d data valid data valid data 1 2 34 56 7 vsync hsync pixclk data[7:0] valid data valid data valid data 1 2 34 56 7
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 51 electrical characteristics hclk = ahb system clock, thclk = period for hclk, tp = period of csi_pixclk the limitation on pixel clock rise time /fall time is not specified. it should be calculated from the hold time and setup time based on the following assumptions: rising-edge latch data: max rise time allowed = (positive duty cycle ? hold time) max fall time allowed = (negative duty cycle ? setup time) in most of case, duty cycle is 50/50, therefore: max rise time = (period/2 ? hold time) max fall time = (period/2 ? setup time) for example: given pixel clock period = 10 ns, duty cycle = 50/50, hold time = 1 ns, setup time = 1 ns. positive duty cycle = 10/2 = 5 ns max rise time allowed = 5 ?1 = 4 ns negative duty cycle = 10/2 = 5 ns max fall time allowed = 5 ?1 = 4 ns falling-edge latch data: max fall time allowed = (negative duty cycle ? hold time) max rise time allowed = (positive duty cycle ? setup time) 4.2.5.2 non-gated clock mode timing in non-gated mode only, the vsync, and pixclk signa ls are used; the hsync signal is ignored. figure 3 and figure 4 show the different clock edge timing of csi and sensor in non-gated mode. table 3 is the parameter value. figure 11 and figure 12 show the non-gated clock mode timings of csi, and table 22 lists the timing parameters. table 21. gated clock mode timing parameters number parameter minimum maximum unit 1 csi_vsync to csi_hsync 9*t hclk ?ns 2 csi_hsync to csi_pixclk 3 (tp/2)-3 ns 3 csi_d setup time 1 ? ns 4 csi_d hold time 1 ? ns 5 csi_pixclk high time t hclk ?ns 6 csi_pixclk low time t hclk ?ns 7 csi_pixclk frequency 0 hclk/2 mhz
i.mx27 and i.mx27l data sheet, rev. 1.3 52 freescale semiconductor electrical characteristics figure 11 shows sensor output data on the pixel clock fal ling edge. the csi latches data on the pixel clock rising edge. figure 11. csi timing diagram, non-gated, pixclk?sensor data at falling edge, latch data at rising edge figure 12 shows sensor output data on the pixel clock risi ng edge. the csi latches data on the pixel clock falling edge. figure 12. csi timing diagram, non-gated, pixclk?sensor data at rising edge, latch data at falling edge table 22. non-gated clock mode parameters number parameter minimum maximum unit ? csi_vsync to csi_pixclk 9*t hclk ?ns ? csi_d setup time 1 ? ns vsync pixclk data[7:0] valid data valid data valid data 23 45 6 1 vsync pixclk data[7:0] valid data valid data valid data 1 23 4 6 5
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 53 electrical characteristics hclk = ahb system clock, thclk = period of hclk 4.2.6 configurable serial peripheral interface (cspi) this section describes the electrical information of the cspi. 4.2.6.1 cspi timing figure 13 and figure 14 show the master mode and slave mode timings of cspi, and table 23 lists the timing parameters. ? csi_d hold time 1 ? ns ? csi_pixclk high time t hclk ?ns ? csi_pixclk low time t hclk ?ns ? csi_pixclk high time 0 hclk/2 mhz table 22. non-gated clock mode parameters (continued) number parameter minimum maximum unit
i.mx27 and i.mx27l data sheet, rev. 1.3 54 freescale semiconductor electrical characteristics 4.3 timing diagrams figure 13 and figure 14 depict the master mode and slave mode timing diagrams of the cspi and table 23 lists the timing parameters. the values shown in timing diagrams were tested using a worst case core voltage of 1.1 v, slow pad voltage of 2.68 v, and fast pad voltage of 1.65 v. figure 13. cspi master mode timing diagram figure 14. cspi slave mode timing diagram t1 t10 t3 t2 ssn sclk mosi miso cspi1_rdy (input) (output) t8 t6 t4 t4 t5 t7 t9 (output) t11 t12 t13 t1? t10 t3? t2? sclk miso mosi t4 t4 t5? t7? (input) t11 t12 t13 t6? ssn (input)
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 55 electrical characteristics table 23. cspi interface timing parameters id num parameter description symbol minimum maximum units t1 cspi master sclk cycle time t clko 45.12 - ns t2 cspi master sclk high time t clkoh 22.65 ? ns t3 cspi master sclk low time t clkol 22.47 ? ns t1? cspi slave sclk cycle time t clki 60.2 ? ns t2? cspi slave sclk high time t clkih 30.1 ? ns t3? cspi slave sclk low time t clkil 30.1 ? ns t4 cspi sclk transition time t pr 1 1 the output sclk transition time is tested with 25 pf drive. 2.6 8.5 ns t5 ssn output pulse width t wsso 2t sclk 2 +t wait 3 2 t sclk = cspi clock period 3 t wait = wait time as per the sample period control register value. ?? t5? ssn input pulse width t wssi t per 4 4 t per = cspi reference baud rate clock period (perclk2) ?? t6 ssn output asserted to first sclk edge (ss output setup time) t ssso 3t sclk ?? t6? ssn input asserted to first sclk edge (ss input setup time) t sssi t per + 20 ns ? ? t7 cspi master: last sclk edge to ssn deasserted (ss output hold time) t hsso 2t sclk ?? t7? cspi slave: last sclk edge to ssn deasserted (ss input hold time) t hssi 30 ? ns t8 cspi master: cspi1_rdy low to ssn asserted (cspi1_rdy setup time) t srdy 2t per 5t per ? t9 cspi master: ssn deasserted to cspi1_rdy low t hrdy 0?ns t10 output data setup time t sdatao (t clkol or t clkoh or t clkil or t clkih ) - t ipg 5 5 t ipg = cspi main clock ipg_clock period ?? t11 output data hold time t hdatao t clkol or t clkoh or t clkil or t clkih ?? t12 input data setup time t sdatai t ipg + 0.5 ? ns t13 input data hold time t hdatai 5?ns note:
i.mx27 and i.mx27l data sheet, rev. 1.3 56 freescale semiconductor electrical characteristics 4.3.1 direct memory access controller (dmac) after assertion of external dma request the dma burst will start when the corresponding dma channel becomes the current highest priority channel. the ex ternal dma request should be kept asserted until it is serviced by the dmac. one external request will initiate at least one dma burst. the output external grant signal from the dmac is an active-low signal. this signal will be asserted during the time when a dma burst is ongoing for an external dma request, when the following conditions are true: ? the dma channel for which the dma burst is ongoing has requested source as external dma request (as per rssr settings). ? ren and cen bit of this channel are set. ? external dma request is asserted. once the grant is asserted the external dma request will not be sampled until completion of the dma burst. the priority of the external request will become low, for the next consecutive burst, if another dma request signal is asserted. the waveforms are shown for the worst case?that is, smallest burst (1 byte read/write). minimum and maximum timings for the external request and external grant signal are present in the data sheet. figure 15 shows the minimum time for which the external grant signal remains asserted if external dma request is de-asserted immediately after sensing grant signal active. figure 15. assertion of dma external grant signal figure 16 shows the safe maximum time for which external dma request can be kept asserted, after sensing grant signal active such that a new burst is not initiated. figure 16. timing diagram of safe maximums for external request de-assertion ext_dmareq ext_dmagrant t min_assert ext_dmareq data read from external device data written to external device ext_dmagrant t max_write t max_read t max_req_assert note: assuming worst case that the data is read/written from/to external device as per the above waveform.
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 57 electrical characteristics 4.3.2 fast ethernet controller (fec) this section describes the ac timing specifications of the fec. the mii signals are compatible with transceivers operating at a voltage of 3.3 v. 4.3.2.1 mii receive signal timing (fec_rxd[3:0], fec_rx_dv, fec_rx_er, and fec_rx_clk) the receiver functions correctly up to a fec_rx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requirement. in addition, the fec ipg clock frequency must exceed twice the fec_rx_clk frequency. figure 17 shows the mii receive signal timings, and table 25 lists the timing parameters. figure 17. mii receive signal timing diagram table 24. dmac timing parameters parameter description 3.0 v 1.8 v unit wcs bcs wcs bcs t min_assert minimum assertion time of external grant signal 8hclk+8.6 8hclk+2.74 8hclk+7.17 8hclk+3.25 ns t max_req_assert maximum external request assertion time after assertion of grant signal 9hclk?20.66 9hclk?6.7 9hclk?17.96 9hclk?8.16 ns t max_read maximum external request assertion time after first read completion 8hclk?6.21 8hclk?0.77 8hclk?5.84 8hclk?0.66 ns t max_write maximum external request assertion time after first write completion 3hclk?5.87 3hclk?8.83 3hclk?15.9 3hclkv91.2 ns table 25. mii receive signal timing parameters id parameter 1 min max unit m1 fec_rxd[3:0], fec_rx_dv, fec_rx_er to fec_rx_clk setup 5 ? ns m2 fec_rx_clk to fec_rxd[3:0], fec_rx_dv, fec_rx_er hold 5 ? ns m3 fec_rx_clk pulse width high 35% 65% fec_rx_clk period fec_rx_clk (input) fec_rxd[3:0] (inputs) fec_rx_dv fec_rx_er m3 m4 m1 m2
i.mx27 and i.mx27l data sheet, rev. 1.3 58 freescale semiconductor electrical characteristics 4.3.2.2 mii transmit signal timing (fec_txd[3:0], fec_tx_en, fec_tx_er, and fec_tx_clk) the transmitter functions correctly up to a fec_tx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requirement. in addition, th e fec ipg clock frequency must exceed twice the fec_tx_clk frequency. figure 18 shows the mii transmit signal timings, and table 26 lists the timing parameters. figure 18. mii transmit signal timing diagram m4 fec_rx_clk pulse width low 35% 65% fec_rx_clk period note: 1 fec_rx_dv, fec_rx_clk, and fec_rxd0 have the same timing in 10 mbps 7-wire interface mode. table 26. mii transmit signal timing parameters id parameter 1 1 fec_tx_en, fec_tx_clk, and fec_txd0 have the same timing in 10 mbps 7-wire interface mode. min max unit m5 fec_tx_clk to fec_txd[3:0], fec_tx_en, fec_tx_er invalid 5 ? ns m6 fec_tx_clk to fec_txd[3:0], fec_tx_en, fec_tx_er valid ? 20 ns m7 fec_tx_clk pulse width high 35% 65% fec_tx_clk period m8 fec_tx_clk pulse width low 35% 65% fec_tx_clk period note: table 25. mii receive signal timing parameters (continued) id parameter 1 min max unit fec_tx_clk (input) fec_txd[3:0] (outputs) fec_tx_en fec_tx_er m7 m8 m5 m6
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 59 electrical characteristics 4.3.2.3 mii asynchronous inputs signal timing (fec_crs and fec_col) figure 19 shows the mii asynchronous input timings, and table 27 lists the timing parameters. figure 19. mii asynchronous inputs signal timing diagram 4.3.2.4 mii serial management channel timing (fec_mdio and fec_mdc) the fec functions correctly with a maximum md c frequency of 2.5 mhz. the mdc frequency should be equal to or less than 2.5 mhz to be compliant with ieee 802.3 mii specification. however the fec can function correctly with a maximum mdc frequency of 15 mhz. figure 20 shows the mii serial management channel timings, and table 28 lists the timing parameters. figure 20. mii serial management channel timing diagram table 27. mii asynchronous inputs signal timing parameter id parameter min max unit m9 1 1 fec_col has the same timing in 10 mbit 7-wire interface mode. fec_crs to fec_col minimum pulse width 1.5 ? fec_tx_clk period note: fec_crs, fec_col m9 fec_mdc (output) fec_mdio (output) m14 m15 m10 m11 m12 m13 fec_mdio (input)
i.mx27 and i.mx27l data sheet, rev. 1.3 60 freescale semiconductor electrical characteristics 4.3.3 inter ic communication (i 2 c) this section describes the electrical information of the i 2 c module. 4.3.3.1 i 2 c module timing the i2c communication protocol consists of seven elements: start, data source/recipient, data direction, slave acknowledge, da ta, data acknowledge, and stop. figure 21 shows the timing of the i 2 c module. table 29 lists the i2c module timing parameters. figure 21. i 2 c bus timing diagram table 28. mii serial management channel timing parameters id parameter min max unit m10 fec_mdc falling edge to fec_mdio output invalid (minimum propagation delay) 0 ? ns m11 fec_mdc falling edge to fec_mdio output valid (max propagation delay) ? 5 ns m12 fec_mdio (input) to fec_mdc rising edge setup 18 ? ns m13 fec_mdio (input) to fec_mdc rising edge hold 0 ? ns m14 fec_mdc pulse width high 40% 60% fec_mdc period m15 fec_mdc pulse width low 40% 60% fec_mdc period table 29. i2c module timing parameters id parameter 1.8 v +/?0.10 v 3.0 v +/?0.30 v unit min max min max ? scl clock frequency 0 100 0 100 khz ic1 hold time (repeated) start condition 114.8 ? 111.1 ? ns ic2 data hold time 0 69.7 0 72.3 ns ic3 data setup time 3.1 ? 1.76 ? ns ic4 high period of the scl clock 69.7 ? 68.3 ? ns ic5 low period of the scl clock 336.4 ? 335.1 ? ns ic6 setup time for stop condition 110.5 ? 111.1 ? ns ic1 ic6 sda scl ic3 ic2 ic5 ic4
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 61 electrical characteristics 4.3.4 jtag controller (jtagc) this section details the electrical characteristics for the jtagc module. figure 22 shows the jtagc test clock input timing; figure 23 shows the jtagc boundary scan timing; figure 24 shows the jtagc test access port; figure 25 shows the jtagc trst timing; and table 30 lists the jtagc timing parameters. figure 22. test clock input timing diagram figure 23. boundary scan timing diagram tck (input) j1 j2 j2 j3 j3 tck (input) data (inputs) input data valid output data valid output data valid data (outputs) data (outputs) data (outputs) j5 j4 j6 j7 j6
i.mx27 and i.mx27l data sheet, rev. 1.3 62 freescale semiconductor electrical characteristics figure 24. test access port (tap) diagram figure 25. trst timing diagram table 30. jtagc timing parameters id parameter all frequencies unit min max j1 tck cycle time in crystal mode 30.08 ? ns j2 tck clock pulse width measured at vm 1 15.04 ? ns j3 tck rise and fall times ? 2.0 ns j4 boundary scan input data set-up time 3.5 ? ns j5 boundary scan input data hold time 16.0 ? ns tck (input) tdi, tms (inputs) input data valid output data valid output data valid td0 (outputs) td0 (outputs) td0 (outputs) j9 j8 j10 j11 j10 tck (input) trst (input) j13 j12
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 63 electrical characteristics 4.3.5 liquid crystal display controller module (lcdc) figure 26 and figure 27 depict the timings of the lcdc, and table 31 and table 32 list the timing parameters. figure 26. lcdc non-tft mode timing diagram j6 tck low to output data valid ? 25.0 ns j7 tck low to output high impedance ? 25.0 ns j8 tms, tdi data set-up time 3.5 ? ns j9 tms, tdi data hold time 20.0 ? ns j10 tck low to tdo data valid ? 29.0 ns j11 tck low to tdo high impedance ? 29.0 ns j12 trst assert time 70.0 ? ns j13 trst set-up time to tck low 2.5.0 ? ns note: 1 midpoint voltage table 30. jtagc timing parameters (continued) id parameter all frequencies unit min max line 1 line 2 line n line 1 flm lp lp lsclk ld t1 t2 t3 t4 t5 t6
i.mx27 and i.mx27l data sheet, rev. 1.3 64 freescale semiconductor electrical characteristics figure 27. lcdc tft mode timing diagram table 31. lcdc non-tft mode timing parameters id description min max unit t1 pixel clock period 22.5 1000 ns t2 lp width 1 ? t 1 1 t is pixel clock period. t3 ld setup time 5 ? ns t4 ld hold time 5 ? ns t5 wait between lp and flm rising edge 2 ? t 1 t6 wait between last data and lp rising edge 1 ? t 1 note: table 32. lcdc tft mode timing parameters id description min ma unit t1 pixel clock period 22.5 1000 ns t2 hsync width 1 ? t 1 t3 ld setup time 5 ? ns t4 ld hold time 5 ? ns t5 delay from the end of hsync to the beginning of the oe pulse. 3 ? t 1 t6 delay from end of oe to the beginning of the hsync pulse. 1 ? t 1 t6 oe t5 line 1 line 2 line n line 1 vsync hsync lsclk ld t1 t2 t3 t4 hsync
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 65 electrical characteristics 4.3.6 memory stick host controller (mshc) figure 30 , figure 28 , and figure 29 show the mshc timings. table 33 and table 34 list the timing parameters. note the i.mx27l does not contain an mshc module. figure 28. transfer operation timing diagram (serial) 1 t is pixel clock period. tsclkc mshc_sclk tbssu tbsh tdsu tdh mshc_bs mshc_data (output) tdd mshc_data (input)
i.mx27 and i.mx27l data sheet, rev. 1.3 66 freescale semiconductor electrical characteristics figure 29. transfer operation timing diagram (parallel) figure 30. mshc_clk timing diagram table 33. serial interface timing parameters signal parameter symbol standards unit min. max. mshc_sclk cycle tsclkc 50 ? ns h pulse length tsclkwh 15 ? ns l pulse length tsclkwl 15 ? ns rise time tsclkr ? 10 ns fall time tsclkf ? 10 ns tsclkc mshc_sclk tbssu tbsh tdsu tdh mshc_bs mshc_data (output) tdd mshc_data (input) tsclkwh tsclkwl tsclkc tsclkr tsclkf mshc_sclk
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 67 electrical characteristics 4.3.7 nand flash controller interface (nfc) figure 31 , figure 32 , figure 33 , and figure 34 show the relative timing requirements among different signals of the nfc at module level, and table 35 lists the timing parameters. the nand flash controller (nfc) timing parameters are based on the internal nfc clock generated by the clock controller module, where time t is the period of the nfc clock in ns. the relationship between the nfc clock and the external timing parameters of the nfc is provided in table 35 . table 35 also provides two examples of external timing parameters with nfc clock frequencies of 22.17 mhz and 33.25 mhz. assuming a 266 mhz fclk (cpu clock), nfcdiv should be set to divide-by-12 to generate a 22.17 mhz nfc clock and divide-by-8 to generate a 33.25 mhz nfc clock. the user should compare the parameters of the se lected nand flash memory with the nfc external timing parameters to determine the proper nfc cloc k. the maximum nfc clock allowed is 66 mhz. it should also be noted that the default nfc clock on power up is 16.63 mhz. mshc_bs setup time tbssu 5 ? ns hold time tbsh 5 ? ns mshc_data setup time tdsu 5 ? ns hold time tdh 5 ? ns output delay time tdd ? 15 ns table 34. parallel interface timing parameters signal parameter symbol standards unit min max mshc_sclk cycle tsclkc 25 ? ns h pulse length tsclkwh 5 ? ns l pulse length tsclkwl 5 ? ns rise time tsclkr ? 10 ns fall time tsclkf ? 10 ns mshc_bs setup time tbssu 8 ? ns hold time tbsh 1 ? ns mshc_data setup time tdsu 8 ? ns hold time tdh 1 ? ns output delay time tdd ? 15 ns table 33. serial interface timing parameters (continued) signal parameter symbol standards unit min. max.
i.mx27 and i.mx27l data sheet, rev. 1.3 68 freescale semiconductor electrical characteristics figure 31. command latch cycle timing diagram figure 32. address latch cycle timing diagram nfcle nfce nfwe nfale nfio[7:0] command nf9 nf8 nf1 nf2 nf5 nf3 nf4 nf6 nf7 nfcle nfce nfwe nfale nfio[7:0] address nf5 nf4 nf6 nf7 nf9 nf8 nf1 nf3 address time it takes for sw to issue the next address command
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 69 electrical characteristics figure 33. write data latch timing diagram figure 34. read data latch timing diagram table 35. nfc target timing parameters id parameter symbol relationship to nfc clock period (t) nfc clock 22.17 mhz t = 45 ns nfc clock 33.25 mhz t = 30 ns unit min max min max min max nf1 nfcle setup time tcls t ? 45 ? 30 ? ns nf2 nfcle hold time tclh t ? 45 ? 30 ? ns nf3 nfce setup time tcs t ? 45 ? 30 ? ns nf4 nfce hold time tch t ? 45 ? 30 ? ns nf5 nf_wp pulse width twp t ? 45 ? 30 ? ns nfcle nfce nfwe nfale nfio[15:0] data to flash nf1 nf3 nf5 nf11 nf10 nf6 nf9 nf8 nf4 nfcle nfce nfre nfrb nfio[15:0] data from flash nf13 nf15 nf14 nf17 nf12 nf16 nf3
i.mx27 and i.mx27l data sheet, rev. 1.3 70 freescale semiconductor electrical characteristics note high is defined as 80% of signal value and low is defined as 20% of signal value. all timings are listed according to this nfc clock frequency (multiples of nfc clock period) ex cept nf16, which is not nfc clock related. the read data is generated by the nand flash device and sampled with the internal nfc clock. nf6 nfale setup time tals t ? 45 ? 30 ? ns nf7 nfale hold time talh t ? 45 ? 30 ? ns nf8 data setup time tds t ? 45 ? 30 ? ns nf9 data hold time tdh t ? 45 ? 30 ? ns nf10 write cycle time twc 2t ? 90 ? 60 ? ns nf11 nfwe hold time twh t ? 45 ? 30 ? ns nf12 ready to nfre low trr 4t ? 180 ? 120 ? ns nf13 nfre pulse width trp 1.5t ? 67.5 ? 45 ? ns nf14 read cycle time trc 2t ? 90 ? 60 ? ns nf15 nfre high hold time treh 0.5t ? 22.5 ? 15 ? ns nf16 data setup on read tdsr 15 ? 15 ? 15 ? ns nf17 data hold on read tdhr 0 ? 0 ? 0 ? ns table 35. nfc target timing parameters (continued) id parameter symbol relationship to nfc clock period (t) nfc clock 22.17 mhz t = 45 ns nfc clock 33.25 mhz t = 30 ns unit min max min max min max
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 71 electrical characteristics 4.3.8 personal computer memory card international association (pcmcia) figure 35 and figure 36 show the timings pertaining to the pcmc ia module, each of which is an example of one clock of strobe setup time and one clock of strobe hold time. table 36 lists the timing parameters. figure 35. write accesses timing diagram?psht=1, psst=1 hclk haddr addr 1 control control 1 hwdata data write 1 hready hresp okay okay okay a[25:0] addr 1 d[15:0] data write 1 wait reg reg oe/we/iord/iowr ce1/ce2 rd/wr poe psst psht psl
i.mx27 and i.mx27l data sheet, rev. 1.3 72 freescale semiconductor electrical characteristics figure 36. read accesses timing diagram?psht=1, psst=1 table 36. pcmcia write and read timing parameters symbol parameter min max unit psht pcmcia strobe hold time 0 63 clock psst pcmcia strobe set up time 1 63 clock psl pcmcia strobe length 1 128 clock hclk haddr addr 1 control control 1 rwdata data read 1 hready hresp okay okay okay a[25:0] addr 1 d[15:0] wait reg reg oe/we/iord/iowr ce1/ce2 rd/wr poe psst psht psl
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 73 electrical characteristics 4.3.9 sdram (ddr and sdr) memory controller figure 37 , figure 38 , figure 39 , figure 40 , figure 41 , and figure 42 depict the timings pertaining to the esdctl module, which interfaces mobile ddr or sdr sdram. table 37 , table 38 , table 39 , table 40 , table 41 , and table 42 list the timing parameters. figure 37. sdram read cycle timing diagram table 37. ddr/sdr sdram read cycle timing parameters id parameter symbol min max unit sd1 sdram clock high-level width tch 3.4 4.1 ns sd2 sdram clock low-level width tcl 3.4 4.1 ns sd3 sdram clock cycle time tck 7.5 ? ns sd4 cs, ras, cas, we, dqm, cke setup time tcms 2.0 ? ns sd5 cs, ras, cas, we, dqm, cke hold time tcmh 1.8 ? ns sdclk we addr dq dqm col/ba data cs cas ras note: cke is high during the read/write cycle. sd4 sd1 sd3 sd2 sd4 sd4 sd4 sd4 sd5 sd5 sd5 sd5 sd5 sd6 sd7 sd10 sd8 sd9 sdclk row/ba
i.mx27 and i.mx27l data sheet, rev. 1.3 74 freescale semiconductor electrical characteristics note sdr sdram clk parameters are being measured from the 50% point?that is, high is defined as 50% of signal value and low is defined as 50% of signal value. sd1 + sd2 does not exceed 7.5 ns for 133 mhz. the timing parameters are similar to the ones used in sdram data sheets?that is, table 37 indicates sdram requirements. all output signals are driven by the esdctl at the negative edge of sdclk and the parameters are measured at maximum memory frequency. sd6 address setup time tas 2.0 ? ns sd7 address hold time tah 1.8 ? ns sd8 sdram access time tac ? 6.47 ns sd9 data out hold time 1 toh 1.8 ? ns sd10 active to read/write command period trc 10 ? clock note: 1 timing parameters are relevant only to sdr sdram. for the specific ddr sdram data related timing parameters, see ta b l e 4 1 and ta b l e 4 2 . table 37. ddr/sdr sdram read cycle timing parameters (continued) id parameter symbol min max unit
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 75 electrical characteristics figure 38. sdr sdram write cycle timing diagram table 38. sdr sdram write timing parameters id parameter symbol min max unit sd1 sdram clock high-level width tch 3.4 4.1 ns sd2 sdram clock low-level width tcl 3.4 4.1 ns sd3 sdram clock cycle time tck 7.5 ? ns sd4 cs, ras, cas, we, dqm, cke setup time tcms 2.0 ? ns sd5 cs, ras, cas, we, dqm, cke hold time tcmh 1.8 ? ns sd6 address setup time tas 2.0 ? ns sd7 address hold time tah 1.8 ? ns sd11 precharge cycle period 1 trp 1 4 clock sd12 active to read/write command delay 1 trcd 1 8 clock cs cas we ras addr dq dqm ba row / ba col/ba data sd4 sd4 sd4 sd4 sd5 sd5 sd5 sd5 sd7 sd6 sd12 sd13 sd14 sd11 sdclk sd1 sd3 sd2 sdclk
i.mx27 and i.mx27l data sheet, rev. 1.3 76 freescale semiconductor electrical characteristics note sdr sdram clk parameters are being measured from the 50% point?that is, high is defined as 50% of signal value and low is defined as 50% of signal value. the timing parameters are similar to the ones used in sdram data sheets?that is, table 38 indicates sdram requirements. all output signals are driven by the esdctl at the negative edge of sdclk and the parameters are measured at maximum memory frequency. figure 39. sdram refresh timing diagram sd13 data setup time tds 2.0 ? ns sd14 data hold time tdh 1.3 ? ns note: 1 sd11 and sd12 are determined by sdram controller register settings. table 39. sdram refresh timing parameters id parameter symbol min max unit sd1 sdram clock high-level width tch 3.4 4.1 ns sd2 sdram clock low-level width tcl 3.4 4.1 ns table 38. sdr sdram write timing parameters (continued) id parameter symbol min max unit cs cas we ras addr ba row/ba sd6 sd7 sd11 sd10 sd10 sdclk sd1 sd2 sdclk sd3
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 77 electrical characteristics note sdr sdram clk parameters are being measured from the 50% point?that is, high is defined as 50% of signal value and low is defined as 50% of signal value. the timing parameters are similar to the ones used in sdram data sheets?that is, table 39 indicates sdram requirements. all output signals are driven by the esdctl at the negative edge of sdclk and the parameters are measured at maximum memory frequency. sd3 sdram clock cycle time tck 7.5 ? ns sd6 address setup time tas 1.8 ? ns sd7 address hold time tah 1.8 ? ns sd10 precharge cycle period 1 trp 1 4 clock sd11 auto precharge command period 1 trc 2 20 clock note: 1 sd10 and sd11 are determined by sdram controller register settings. table 39. sdram refresh timing parameters (continued) id parameter symbol min max unit
i.mx27 and i.mx27l data sheet, rev. 1.3 78 freescale semiconductor electrical characteristics figure 40. sdram self-refresh cycle timing diagram note the clock continues to run unless both ckes are low. then the clock is stopped in low state. table 40. sdram self-refresh cycle timing parameters id parameter symbol min max unit sd16 cke output delay time tcks 1.8 ? ns sdclk cs cas ras addr ba we cke don?t care sd16 sd16
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 79 electrical characteristics figure 41. mobile ddr sdram write cycle timing diagram note sdram clk and dqs related parameters are being measured from the 50% point?that is, high is defined as 50% of signal value and low is defined as 50% of signal value. the timing parameters are similar to the ones used in sdram data sheets?that is, table 41 indicates sdram requirements. all output signals are driven by the esdctl at the negative edge of sdclk and the parameters are measured at maximum memory frequency. table 41. mobile ddr sdram write cycle timing parameters 1 1 test condition: measured using delay line 5 programmed as follows: esdcdly5[15:0] = 0x0703. id parameter symbol min max unit sd17 dq and dqm setup time to dqs tds 0.95 ? ns sd18 dq and dqm hold time to dqs tdh 0.95 ? ns sd19 write cycle dqs falling edge to sdclk output delay time. tdss 1.8 ? ns sd20 write cycle dqs falling edge to sdclk output hold time. tdsh 1.8 ? ns note: sdclk sdclk dqs (output) dq (output) dqm (output) data data data data data data data data dm dm dm dm dm dm dm dm sd17 sd17 sd17 sd17 sd18 sd18 sd18 sd18 sd19 sd20
i.mx27 and i.mx27l data sheet, rev. 1.3 80 freescale semiconductor electrical characteristics figure 42. mobile ddr sdram dq versus dqs and sdclk read cycle timing diagram note sdram clk and dqs related parameters are being measured from the 50% point?that is, high is defined as 50% of signal value and low is defined as 50% of signal value. the timing parameters are similar to the ones used in sdram data sheets?that is, table 42 indicates sdram requirements. all output signals are driven by the esdctl at the negative edge of sdclk and the parameters are measured at maximum memory frequency. 4.3.9.1 sdhc electrical dc characteristics table 43 lists the sdhc electrical dc characteristics. table 42. mobile ddr sdram read cycle timing parameters id parameter symbol min max unit sd21 dqs?dq skew (defines the data valid window in read cycles related to dqs). tdqsq ? 0.85 ns sd22 dqs dq hold time from dqs tqh 2.3 ? ns sd23 dqs output access time from sdclk posedge tdqsck ? 6.7 ns table 43. sdhc electrical dc characteristics id parameter min max unit comments general sd10 peak voltage on all lines ?0.3 v dd + 0.3 v ? all inputs sd11 input leakage current ?10 10 a? all outputs sd12 output leakage current ?10 10 a? power supply sdclk sdclk dqs (input) dq (input) data data data data data data data data sd23 sd21 sd22
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 81 electrical characteristics sd13 supply voltage (low voltage) 1.65 1.95 v 1.95 ~2.7 v is not supported. sd14 supply voltage (high voltage) 2.7 3.6 v sd15 power up time ? 250 ms ? sd16 supply current 100 ? ma ? bus signal line load sd17 pull-up resistance 10 100 k internal pu sd18 open drain resistance na na k for mmc cards only open drain signal level ? sd19 output high voltage v dd ? 0.2 ? v i oh =-100 ma sd20 output low voltage ? 0.3 v i ol = 2 ma push-pull signal levels (high voltage) sd21 output high voltage 0.75 x v dd ?vi oh =-100 ma @v dd min sd22 output low voltage ? 0.125 x v dd vi ol =100 ma @v dd min sd23 input high voltage 0.625 x v dd v dd + 0.3 v ? sd24 input low voltage v ss ? 0.3 0.25 x v dd v? push-pull signal levels (low voltage) sd25 output high voltage v dd ? 0.2 ? v i oh =-100 ma @v dd min sd26 output low voltage ? 0.2 v i ol =100 ma @v dd min sd27 input high voltage 0.7 x v dd v dd + 0.3 v ? sd28 input low voltage v ss ? 0.3 0.3 x v dd v? table 43. sdhc electrical dc characteristics id parameter min max unit comments
i.mx27 and i.mx27l data sheet, rev. 1.3 82 freescale semiconductor electrical characteristics 4.3.10 smart liquid crystal display controller (slcdc) figure 43 and figure 44 show the timings of the slcdc, and table 44 and table 45 list the timing parameters. figure 43. slcdc timing diagram?serial transfers to lcd device trss trss lcd_clk (lcd_data[6]) sdata (lcd_data[7]) lcd_cs rs lsb msb rs=0 => command data, rs=1=> display data lcd_clk (lcd_data[6]) sdata (lcd_data[7]) lcd_cs rs lsb msb rs=0 => command data, rs=1=> display data this diagram illustrates the timing when the sckpol = 1, cspol = 0 this diagram illustrates the timing when the sckpol = 0, cspol = 0 lcd_clk (lcd_data[6]) sdata (lcd_data[7]) lcd_cs rs lsb msb rs=0 => command data, rs=1=> display data this diagram illustrates the timing when the sckpol = 1, cspol = 1 lcd_clk (lcd_data[6]) sdata (lcd_data[7]) lcd_cs rs lsb msb rs=0 => command data, rs=1=> display data this diagram illustrates the timing when the sckpol = 0, cspol = 1 tcss tcyc tds tcsh tdh tcl tch trsh trss tcss tcyc tds tcsh tdh tcl tch trsh tcss tcyc tds tcsh tdh tcl tch trsh tcss tcyc tds tcsh tdh tcl tch trsh trss
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 83 electrical characteristics figure 44. slcdc timing diagram?para llel transfers to lcd device table 44. slcdc serial interface timing parameters symbol parameter min typical max units t css chip select setup time (t cyc / 2) ( ) t prop ??ns t csh chip select hold time (t cyc / 2) ( ) t prop ??ns t cyc serial clock cycle time 39 ( ) t prop ? 2641 ns t cl serial clock low pulse 18 ( ) t prop ??ns t ch serial clock high pulse 18 ( ) t prop ??ns t ds data setup time (t cyc / 2) ( ) t prop ??ns t dh data hold time (t cyc / 2) ( ) t prop ??ns t rss register select setup time (15 * t cyc / 2) ( ) t prop ??ns t rsh register select hold time (t cyc / 2) ( ) t prop ??ns table 45. slcdc parallel interface timing parameters symbol parameter min typical max units t cyc parallel clock cycle time 78 ( ) t prop ? 4923 ? t ds data setup time (t cyc / 2) ( ) t prop ??? t dh data hold time (t cyc / 2) ( ) t prop ??? lcd_clk lcd_data[15:0] lcd_rs command data lcd_cs display data trsh trss tds tdh tcyc lcd_clk lcd_data[15:0] lcd_rs command data lcd_cs display data trsh trss tds tdh tcyc this diagram illustrates the timing when cspol=0 this diagram illustrates the timing when cspol=1
i.mx27 and i.mx27l data sheet, rev. 1.3 84 freescale semiconductor electrical characteristics 4.3.11 synchronous serial interface (ssi) this section describes the electrical information of ssi. 4.3.11.1 ssi transmitter timing with internal clock figure 45 and figure 46 show the ssi transmitter timing with internal clock, and table 46 lists the timing parameters. figure 45. ssi transmitter with internal clock timing diagram t rss register select setup time (t cyc / 2) ( ) t prop ??? t rsh register select hold time (t cyc / 2) ( ) t prop ??? table 45. slcdc parallel interface timing parameters (continued) symbol parameter min typical max units ss19 ad1_txc ad1_txfs (bl) ad1_txfs (wl) ss1 ad1_txd ad1_rxd ss2 ss4 ss3 ss5 ss6 ss8 ss10 ss12 ss14 ss18 ss15 ss17 ss16 ss43 ss42 note: srxd input in synchronous mode only (output) (output) (output) (output) (input)
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 85 electrical characteristics figure 46. ssi transmitter with internal clock timing diagram table 46. ssi transmitter with internal clock timing parameters id parameter min max unit internal clock operation ss1 (tx/rx) ck clock period 81.4 ? ns ss2 (tx/rx) ck clock high period 36.0 ? ns ss3 (tx/rx) ck clock rise time ? 6 ns ss4 (tx/rx) ck clock low period 36.0 ? ns ss5 (tx/rx) ck clock fall time ? 6 ns ss6 (tx) ck high to fs (bl) high ? 15.0 ns ss8 (tx) ck high to fs (bl) low ? 15.0 ns ss10 (tx) ck high to fs (wl) high ? 15.0 ns ss12 (tx) ck high to fs (wl) low ? 15.0 ns ss14 (tx/rx) internal fs rise time ? 6 ns ss15 (tx/rx) internal fs fall time ? 6 ns ss16 (tx) ck high to stxd valid from high impedance ? 15.0 ns ss17 (tx) ck high to stxd high/low ? 15.0 ns ss18 (tx) ck high to stxd high impedance ? 15.0 ns ss19 stxd rise/fall time ? 6 ns ss19 dam1_t_clk dam1_t_fs (bl) dam1_t_fs (wl) ss1 dam1_txd dam1_rxd ss2 ss4 ss3 ss5 ss6 ss8 ss10 ss12 ss14 ss18 ss15 ss17 ss16 ss42 note: srxd input in synchronous mode only (output) (output) (output) (output) (input) ss43
i.mx27 and i.mx27l data sheet, rev. 1.3 86 freescale semiconductor electrical characteristics ? all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. ? all timings are on audmux pads when ssi is being used for data transfer. ? ?tx? and ?rx? refer to the transmit and receive sections of the ssi. ? for internal frame sync operation using external clock, the fs timing will be same as that of tx data (for example, during ac97 mode of operation). 4.3.11.2 ssi receiver timing with internal clock figure 47 and figure 48 show the ssi receiver timing with internal clock, and table 47 lists the timing parameters. figure 47. ssi receiver with internal clock timing diagram synchronous internal clock operation ss42 srxd setup before (tx) ck falling 10.0 ? ns ss43 srxd hold after (tx) ck falling 0 ? ns ss52 loading ? 25 pf table 46. ssi transmitter with internal clock timing parameters (continued) id parameter min max unit ss50 ss48 ad1_txc ad1_txfs (bl) ad1_txfs (wl) ad1_rxd ad1_rxc ss1 ss4 ss2 ss51 ss20 ss21 ss49 ss7 ss9 ss11 ss13 ss47 (output) (output) (output) (input) (output) ss3 ss5
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 87 electrical characteristics figure 48. ssi receiver with internal clock timing diagram table 47. ssi receiver with internal clock timing parameters id parameter min max unit internal clock operation ss1 (tx/rx) ck clock period 81.4 ? ns ss2 (tx/rx) ck clock high period 36.0 ? ns ss3 (tx/rx) ck clock rise time ? 6 ns ss4 (tx/rx) ck clock low period 36.0 ? ns ss5 (tx/rx) ck clock fall time ? 6 ns ss7 (rx) ck high to fs (bl) high ? 15.0 ns ss9 (rx) ck high to fs (bl) low ? 15.0 ns ss11 (rx) ck high to fs (wl) high ? 15.0 ns ss13 (rx) ck high to fs (wl) low ? 15.0 ns ss20 srxd setup time before (rx) ck low 10.0 ? ns ss21 srxd hold time after (rx) ck low 0 ? ns oversampling clock operation ss47 oversampling clock period 15.04 ? ns ss48 oversampling clock high period 6 ? ns ss50 ss48 dam1_t_clk dam1_t_fs (bl) dam1_t_fs (wl) dam1_rxd dam1_r_clk ss3 ss1 ss4 ss2 ss5 ss51 ss20 ss21 ss49 ss7 ss9 ss11 ss13 ss47 (output) (output) (output) (input) (output)
i.mx27 and i.mx27l data sheet, rev. 1.3 88 freescale semiconductor electrical characteristics note all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. all timings are on audmux pads when ssi is being used for data transfer. ?tx? and ?rx? refer to the transmit and receive sections of the ssi. for internal frame sync operation using external clock, the fs timing is the same as that of tx data, for example, during the ac97 mode of operation. 4.3.11.3 ssi transmitter timing with external clock figure 49 and figure 50 show the ssi transmitter timing with external clock, and table 48 lists the timing parameters. figure 49. ssi transmitter with external clock timing diagram ss49 oversampling clock rise time ? 3 ns ss50 oversampling clock low period 6 ? ns ss51 oversampling clock fall time ? 3 ns table 47. ssi receiver with internal clock timing parameters (continued) id parameter min max unit ss45 ss33 ss24 ss26 ss25 ss23 ad1_txc ad1_txfs (bl) ad1_txfs (wl) ad1_txd ad1_rxd note: srxd input in synchronous mode only ss31 ss29 ss27 ss22 ss44 ss39 ss38 ss37 ss46 (input) (input) (input) (output) (input)
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 89 electrical characteristics figure 50. ssi transmitter with external clock timing diagram table 48. ssi transmitter with external clock timing parameters id parameter min max unit external clock operation ss22 (tx/rx) ck clock period 81.4 ? ns ss23 (tx/rx) ck clock high period 36.0 ? ns ss24 (tx/rx) ck clock rise time ? 6.0 ns ss25 (tx/rx) ck clock low period 36.0 ? ns ss26 (tx/rx) ck clock fall time ? 6.0 ns ss27 (tx) ck high to fs (bl) high ?10.0 15.0 ns ss29 (tx) ck high to fs (bl) low 10.0 ? ns ss31 (tx) ck high to fs (wl) high ?10.0 15.0 ns ss33 (tx) ck high to fs (wl) low 10.0 ? ns ss37 (tx) ck high to stxd valid from high impedance ? 15.0 ns ss38 (tx) ck high to stxd high/low ? 15.0 ns ss39 (tx) ck high to stxd high impedance ? 15.0 ns synchronous external clock operation ss44 srxd setup before (tx) ck falling 10.0 ? ns ss45 srxd hold after (tx) ck falling 2.0 ? ns ss46 srxd rise/fall time ? 6.0 ns ss45 ss33 ss24 ss26 ss25 ss23 dam1_t_clk dam1_t_fs (bl) dam1_t_fs (wl) dam1_txd dam1_rxd note: srxd input in synchronous mode only ss31 ss29 ss27 ss22 ss44 ss39 ss38 ss37 ss46 (input) (input) (input) (output) (input)
i.mx27 and i.mx27l data sheet, rev. 1.3 90 freescale semiconductor electrical characteristics note all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. all timings are on audmux pads when the ssi is being used for data transfer. ?tx? and ?rx? refer to the transmit and receive sections of the ssi. for internal frame sync operation using external clock, the fs timing will be same as that of tx data, for example, during the ac97 mode of operation. 4.3.11.4 ssi receiver timing with external clock figure 51 and figure 52 show the ssi receiver timing with external clock, and table 49 lists the timing parameters. figure 51. ssi receiver with external clock timing diagram ss24 ss34 ss35 ss30 ss28 ss26 ss25 ss23 ad1_txc ad1_txfs (bl) ad1_txfs (wl) ad1_rxd ss40 ss22 ss32 ss36 ss41 (input) (input) (input) (input)
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 91 electrical characteristics figure 52. ssi receiver with external clock timing diagram table 49. ssi receiver with external clock timing parameters id parameter min max unit external clock operation ss22 (tx/rx) ck clock period 81.4 ? ns ss23 (tx/rx) ck clock high period 36.0 ? ns ss24 (tx/rx) ck clock rise time ? 6.0 ns ss25 (tx/rx) ck clock low period 36.0 ? ns ss26 (tx/rx) ck clock fall time ? 6.0 ns ss28 (rx) ck high to fs (bl) high ?10.0 15.0 ns ss30 (rx) ck high to fs (bl) low 10.0 ? ns ss32 (rx) ck high to fs (wl) high ?10.0 15.0 ns ss34 (rx) ck high to fs (wl) low 10.0 ? ns ss35 (tx/rx) external fs rise time ? 6.0 ns ss36 (tx/rx) external fs fall time ? 6.0 ns ss40 srxd setup time before (rx) ck low 10.0 ? ns ss41 srxd hold time after (rx) ck low 2.0 ? ns ss24 ss34 ss35 ss30 ss28 ss26 ss25 ss23 dam1_t_clk dam1_t_fs (bl) dam1_t_fs (wl) dam1_rxd ss40 ss22 ss32 ss36 ss41 (input) (input) (input) (input)
i.mx27 and i.mx27l data sheet, rev. 1.3 92 freescale semiconductor electrical characteristics note all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. all timings are on audmux pads when the ssi is being used for data transfer. ?tx? and ?rx? refer to the transmit and receive sections of the ssi. for internal frame sync operation using external clock, the fs timing will be same as that of tx data, for example, during the ac97 mode of operation. 4.3.12 wireless external interface module (weim) all weim output control signals may be asserted and deasserted by internal clock related to bclk rising edge or falling edge according to corresponding asser tion/negation control fields. address always begins related to bclk falling edge but may be ended both on rising and falling edge in muxed mode according to control register configuration. output data begins related to bcl k rising edge except in muxed mode where both rising and falling edge may be used accordi ng to control register configuration. input data, ecb and dtack all captured according to bclk rising edge time. figure 53 shows the timing of the weim module, and table 50 lists the timing parameters.
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 93 electrical characteristics figure 53. weim bus timing diagram table 50. weim bus timing parameters id parameter 1.8 v unit min max we1 clock fall to address valid 0.68 2.05 ns we2 clock rise/fall to address invalid 0.68 2.49 ns we3 clock rise/fall to cs [x] valid 0.45 2.25 ns we4 clock rise/fall to cs [x] invalid 0.45 2.25 ns we1 we2 we3 we4 we5 we6 we7 we8 we9 we10 we11 we12 we13 we14 we16 we15 we18 we17 we20 we19 we21 we22 we23 bclk (for rising edge timing) bclk (for falling edge timing) address cs[x] rw oe eb[x] lba output data bclk (for rising edge timing) input data weim outputs timing weim inputs timing ecb dtack ... ...
i.mx27 and i.mx27l data sheet, rev. 1.3 94 freescale semiconductor electrical characteristics note high is defined as 80% of signal value and low is defined as 20% of signal value. test conditions: pad voltage, 1.7?1.95 v; pad capacitance, 25 pf. recommended drive strength for all controls, address, and bclk is max high. we5 clock rise/fall to rw valid 0.90 2.60 ns we6 clock rise/fall to rw invalid 0.90 2.60 ns we7 clock rise/fall to oe valid 1.17 3.57 ns we8 clock rise/fall to oe invalid 1.17 3.57 ns we9 clock rise/fall to eb [x] valid 0.73 2.43 ns we10 clock rise/fall to eb [x] invalid 0.73 2.43 ns we11 clock rise/fall to lba valid 1.03 2.84 ns we12 clock rise/fall to lba invalid 1.03 2.84 ns we13 clock rise/fall to output data valid 1.04 4.01 ns we14 clock rise to output data invalid 1.04 4.01 ns we15 input data valid to clock rise, fce=0 6.95 ? ns we16 cloc/k rise to input data invalid, fce=0 2.35 ? ns we17 input data valid to clock rise, fce=1 1.24 ? ns we18 clock rise to input data invalid, fce=1 0.23 ? ns we19 ecb setup time, fce=0 7.23 ? ns we20 ecb hold time, fce=0 2.93 ? ns we21 ecb setup time, fce=1 1.08 ? ns we22 ecb hold time, fce=1 0 ? ns we23 dtack setup time 5.35 ? ns we24 dtack hold time 3.19 ? ns we25 bclk high level width 1 3.0 ? ns we26 bclk low level width 1 3.0 ? ns we27 bclk cycle time 1 7.5 ? ns note: 1 bclk parameters are being measured from the 50% point?that is, high is defined as 50% of signal value and low is defined as 50% of signal value. table 50. weim bus timing parameters (continued) id parameter 1.8 v unit min max
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 95 electrical characteristics figure 54 , figure 55 , figure 34 , figure 57 , figure 58 , and figure 59 show examples of basic weim accesses to external memory devices w ith the timing parameters mentioned in table 50 for specific control parameter settings. figure 54. asynchronous memory timing diagram for read access?wsc=1 figure 55. asynchronous memory timing diagram for write access?wsc=1, ebwa=1, ebwn=1, lbn=1 last valid address v1 v1 bclk addr data rw lba oe eb [y] cs [x] next address we1 we2 we3 we4 we7 we8 we10 we9 we11 we12 we15 we16 last valid address v1 v1 bclk addr data rw lba oe eb [y] cs [x] next address we1 we2 we3 we4 we5 we6 we9 we10 we11 we12 we13 we14
i.mx27 and i.mx27l data sheet, rev. 1.3 96 freescale semiconductor electrical characteristics figure 56. synchronous memory timing diagram for two non-sequential read accesses: wsc=2, sync=1, dol=0 figure 57. synchronous memory timing diagram for burst write access?bcs=1, wsc=4, sync=1, dol=0, psr=1 last valid addr address v1 address v2 v1 v1+2 v2 v2+2 bclk addr ecb data halfword halfword cs[x] rw lba oe eb [y] halfword halfword we1 we2 we4 we7 we8 we9 we10 we11 we12 we15 we15 we16 we16 we17 we17 we18 we18 we3 last valid addr bclk addr data cs [x] rw lba oe eb [y] ecb address v1 v1 v1+4 v1+12 v1+8 we9 we1 we2 we3 we4 we5 we6 we10 we11 we13 we13 we14 we14 we17 we18 we12
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 97 electrical characteristics figure 58. muxed a/d mode timing diagram for asynchronous write access?wsc=7, lba=1, lbn=1, lah=1 figure 59. muxed a/d mode timing diagram for asynchronous read access?wsc=7, lba=1, lbn=1, lah=1, oea=7 4.3.13 usbotg electricals this section describes the electrical information of the usb otg port and host ports. 4.3.14 serial interface in order to support four serial different interfaces, the usbotg transceiver can be configured to operate in one of the following modes: ? dat_se0 bidirectional, 3-wire mode ? dat_se0 unidirectional, 6-wire mode write bclk addr/ rw lba oe eb [y] cs [x] address v1 write data last valid addr m_data we1 we2 we3 we4 we6 we5 we9 we10 we11 we12 we13 we14 bclk addr/ rw lba oe eb [y] cs [x] address v1 read data last valid addr m_data we2 we3 we4 we11 we12 we7 we8 we9 we10 we15 we16 we1
i.mx27 and i.mx27l data sheet, rev. 1.3 98 freescale semiconductor electrical characteristics ? vp_vm bidirectional, 4-wire mode ? vp_vm unidirectional, 6-wire mode 4.3.14.1 dat_se0 bidirectional mode figure 60. usb transmit waveform in dat_se0 bidirectional mode figure 61. usb receive waveform in dat_se0 bidirectional mode table 51. signal definitions?dat_se0 bidirectional mode name direction signal description usb_txoe_b out ? transmit enable, active low usb_dat_vp out in ? tx data when usb_txoe_b is low ? differential rx data when usb_txoe_b is high usb_se0_vm out in ? se0 drive when usb_txoe_b is low ? se0 rx indicator when usb_txoe_b is high usb_dat_vp usb_se0_vm usb_txoe_b usb_dat_vp usb_se0_vm
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 99 electrical characteristics 4.3.14.2 dat_se0 unidirectional mode figure 62. usb transmit waveform in dat_se0 unidirectional mode table 52. otg port timing specification in dat_se0 bidirectional mode parameter signal name direction min max unit conditions/ reference signal tx rise/fall time usb_dat_vp out ? 5.0 ns 50 pf tx rise/fall time usb_se0_vm out ? 5.0 ns 50 pf tx rise/fall time usb_txoe_b out ? 5.0 ns 50 pf tx duty cycle usb_dat_vp out 49.0 51.0 % ? enable delay usb_dat_vp usb_se0_vm in ? 8.0 ns usb_txoe_b disable delay usb_dat_vp usb_se0_vm in ? 10.0 ns usb_txoe_b rx rise/fall time usb_dat_vp in ? 3.0 ns 35 pf rx rise/fall time usb_se0_vm in ? 3.0 ns 35 pf table 53. signal definitions?dat_se0 unidirectional mode name direction signal description usb_txoe_b out transmit enable, active low usb_dat_vp out tx data when usb_txoe_b is low. usb_se0_vm out se0 drive when usb_txoe_b is low. usb_vp1 in buffered data on dp when usb_txoe_b is high. usb_vm1 in buffered data on dm when usb_txoe_b is high. usb_rcv in differential rx data when usb_txoe_b is high. usb_dat_vp usb_se0_vm
i.mx27 and i.mx27l data sheet, rev. 1.3 100 freescale semiconductor electrical characteristics figure 63. usb receive waveform in dat_se0 unidirectional mode 4.3.14.3 vp_vm bidirectional mode table 54. otg port timing specification in dat_se0 unidirectional mode parameter signal name signal source min max unit condition/ reference signal tx rise/fall time usb_dat_vp out ? 5.0 ns 50 pf tx rise/fall time usb_se0_vm out ? 5.0 ns 50 pf tx rise/fall time usb_txoe_b out ? 5.0 ns 50 pf tx duty cycle usb_dat_vp out 49.0 51.0 % ? enable delay usb_dat_vp usb_se0_vm in ? 8.0 ns usb_txoe_b disable delay usb_dat_vp usb_se0_vm in ? 10.0 ns usb_txoe_b rx rise/fall time usb_vp1 in ? 3.0 ns 35 pf rx rise/fall time usb_vm1 in ? 3.0 ns 35 pf rx rise/fall time usb_rcv in ? 3.0 ns 35 pf table 55. signal definitions?vp_vm bidirectional mode name direction signal description usb_txoe_b out ? transmit enable, active low usb_dat_vp out (tx) in (rx) ? tx vp data when usb_txoe_b is low ? rx vp data when usb_txoe_b is high usb_se0_vm out (tx) in (rx) ? tx vm data when usb_txoe_b low ? rx vm data when usb_txoe_b high usb_rcv in ? differential rx data vp, vm, rcv usb_dat_vp/ usb_se0_vm
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 101 electrical characteristics figure 64. usb transmit waveform in vp_vm bidirectional mode figure 65. usb receive waveform in vp_vm bidirectional mode usb_dat_vp usb_txoe_b usb_se0_vm usb_se0_vm usb_dat_vp usb_se0_vm usb_txoe_b usb_se0_vm
i.mx27 and i.mx27l data sheet, rev. 1.3 102 freescale semiconductor electrical characteristics 4.3.14.4 vp_vm unidirectional mode table 56. otg port timing specification in vp_vm bidirectional mode parameter signal name direction min max unit condition/ reference signal tx rise/fall time usb_dat_vp out ? 5.0 ns 50 pf tx rise/fall time usb_se0_vm out ? 5.0 ns 50 pf tx rise/fall time usb_txoe_b out ? 5.0 ns 50 pf tx duty cycle usb_dat_vp out 49.0 51.0 % ? tx high overlap usb_se0_vm out 0.0 ? ns usb_dat_vp tx low overlap usb_se0_vm out ? 0.0 ns usb_dat_vp enable delay usb_dat_vp usb_se0_vm in ? 8.0 ns usb_txoe_b disable delay usb_dat_vp usb_se0_vm in ? 10.0 ns usb_txoe_b rx rise/fall time usb_dat_vp in ? 3.0 ns 35 pf rx rise/fall time usb_se0_vm in ? 3.0 ns 35 pf rx skew usb_dat_vp out ?4.0 +4.0 ns usb_se0_vm rx skew usb_rcv out ?6.0 +2.0 ns usb_dat_vp table 57. signal definitions?vp_vm unidirectional mode name direction signal description usb_txoe_b out transmit enable, active low usb_dat_vp out tx vp data when usb_txoe_b is low usb_se0_vm out tx vm data when usb_txoe_b is low usb_vp1 in rx vp data when usb_txoe_b is high usb_vm1 in rx vm data when usb_txoe_b is high usb_rcv in differential rx data
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 103 electrical characteristics figure 66. usb transmit waveform in vp_vm unidirectional mode figure 67. usb receive waveform in vp_vm unidirectional mode usb_dat_vp usb_txoe_b usb_se0_vm usb_se0_vm usb_vp1 uh1_rxd usb_txoe_b usb_vm1
i.mx27 and i.mx27l data sheet, rev. 1.3 104 freescale semiconductor electrical characteristics table 58. usb timing specification in vp_vm unidirectional mode parameter signal direction min max unit conditions/ reference signal tx rise/fall time usb_dat_vp out ? 5.0 ns 50 pf tx rise/fall time usb_se0_vm out ? 5.0 ns 50 pf tx rise/fall time usb_txoe_b out ? 5.0 ns 50 pf tx duty cycle usb_dat_vp out 49.0 51.0 % ? tx high overlap usb_se0_vm out 0.0 ? ns usb_dat_vp tx low overlap usb_se0_vm out ? 0.0 ns usb_dat_vp enable delay usb_dat_vp usb_se0_vm in ? 8.0 ns usb_txoe_b disable delay usb_dat_vp usb_se0_vm in ? 10.0 ns usb_txoe_b rx rise/fall time usb_vp1 in ? 3.0 ns 35 pf rx rise/fall time usb_vm1 in ? 3.0 ns 35 pf rx skew usb_vp1 out ?4.0 +4.0 ns usb_se0_vm rx skew usb_rcv out ?6.0 +2.0 ns usb_dat_vp
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 105 package information and pinout 5 package information and pinout the i.mx27/mx27l processor is available in a 17 mm 17 mm, 0.65 mm pitch, 404-pin mapbga package and a 19 mm 19 mm, 0.8 mm pitch, 473-pin mapbga package. 5.1 full package outline drawing (17 mm 17 mm) figure 68 shows the package drawings and dimensions of the production package. figure 68. i.mx27/mx27l 17 mm 17 mm full package mapbga: mechanical drawing
i.mx27/i.mx27l block guide, rev. 1.3 106 freescale semiconductor package information and pinout 5.2 pin assignments (17 mm 17 mm) table 59 shows the i.mx27 full 17 17 mm package mapbga pin assignment. table 60 identifies the pin assignments for the ball grid array (bga) for full package. the connections of these pins depend solely upon the user application, however there are a few factory test signals that are not used in a normal application. following is a list of these signals and how they are to be terminated for proper operation of the i.mx27/mx27l processor: ? clkmode[1:0]: to ensure proper operation, leave these signals as no connects. ? osc26m_test: to ensure proper operation, leave this signal as no connect. ? ext_60m: to ensure proper operation, connect this signal to ground. ? ext_266m: to ensure proper operation, connect this signal to ground. ? most of the signals shown in table 60 are multiplexed with other signals. for ease of reference, all of the signals at a particular pad are shown in the form of a compound signal name. please refer to table 3 for complete information on the signal multiplexing schemes of these signals. table 59. i.mx27 full 17 17 mm package mapbga pin assignment 1 2 3 4 5 6 7 8 9 10111213141516 17 18 192021222324 a gnd gnd sd2_ d3_m shc_ data 3_pb 7_pa d sd2_ clk_ mshc _scl k_pb 9_pad csi_d 3_ua rt6_ rts_ pb13_ pa d csi_d 5_pb1 7_pad csi_h sync _uar t5_r ts_p b21_ pa d ssi4_ rxda t_pc 17_pa d ssi1_ rxda t_pc 21_pa d ssi2_ rxda t_gp t5_ti n_pc 25_pa d ssi3_ rxda t_sl cdc2 _rs_ pc29 _pad kp_r ow1_ pa d kp_r ow5_ pa d uart 2_rt s_kp _row 7_pe 4_pa d kp_c ol2_ pa d uart 2_tx d_kp _col 6_pe 6_pa d uart3 _cts_ pe10_ pa d uart1 _cts_ pe14_ pa d rtck_ owir e_pe1 6_pad sd1_ d0_c spi3_ miso _pe1 8_pa d sd1_ cmd_ cspi 3_mo si_pe 22_p ad cspi 1_mi so_ pd3 0_pa d gnd gnd bgndgndspl_ spr_ pa 2 7 _pad csi_d 1_ua rt6_ rxd_ pb11_ pa d csi_m clk_ pb15_ pa d csi_d 7_ua rt5_ rxd_ pb19_ pa d tin_p c15_ pa d ssi4_ clk_ pc19 _pad ssi1_ clk_ pc23 _pad ssi2_ clk_ gpt4 _tin_ pc27 _pad ssi3_ clk_ slcd c2_c lk_p c31_ pa d kp_r ow3_ pa d i2c_c lk_p d18_ pa d kp_c ol0_ pa d kp_c ol4_ pa d uart 3_tx d_pe 8_pa d uart1 _txd_ pe12_ pa d tdi_p ad tms_ pa d sd1_ d2_p e20_ pa d cspi 1_rd y_pd 25_p ad cspi 1_s s0_ pd2 8_pa d gnd gnd csd2_ d0_m shc_ data 0_pb 4_pa d con tra st_ pa 3 0 _pa d csi_ d0_u art6 _txd _pb1 0_pa d sd2_ cmd_ mshc _bs_ pb8_ pa d sd2_ d2_m shc_ data2 _pb6_ pa d ssi3_ txda t_sl cdc2 _cs_ pc30 _pad kp_r ow2_ pa d pwm o_pe 5_pa d uart 1_rt s_pe 15_pa d trst _b_p ad cspi1 _ss1_ pd27_ pa d cspi1 _mosi _pd31 _pad cspi2 _ss1_ usbh 2_dat a3_pd 20 usb h1_o e_b_ pb27 _pad
i.mx27/i.mx27l block guide, rev. 1.3 freescale semiconductor 107 package information and pinout dhsy nc_p a28_ pa d ps_ pa 2 6 _pa d oe_a cd_p a31_ pa d cspi 2_s s2_ usb h2_ data 4_p d19 cspi 2_s clk _us bh2 _dat a0_ pd2 2 usbh 1_tx dp_u art4 _cts _pb2 9 e rev_ pa 2 4 _pad ld1 6_pa 22_p ad sd2_ d1_m shc_ data 1_pb 5_pa d csi_d 2_ua rt6_ cts_ pb12_ pa d csi_p ixclk _pb16 _pad tout _pc1 4_pa d ssi1_ txda t_pc 22_pa d ssi3_ fs_s lcdc 2_d0_ pc28 _pad kp_r ow4_ pa d uart 2_ct s_kp _col 7_pe 3_pa d kp_c ol3_ pa d uart 2_rx d_kp _row 6_pe 7_pa d uart 3_rt s_pe 11_pa d tdo_ pa d sd1_ d1_p e19_ pa d sd1_d 3_csp i3_ss _pe21 _pad usbh 1_fs_ uart4 _rts_ pb26_ pa d cspi 1_ss 2_us bh2_ data 5_pd 26 cspi 2_mo si_u sbh2 _dat a1_p d24 usb h1_ rxd p_u art 4_r xd_ pb3 1 fld14 _pa2 0_pa d ld1 0_pa 16_p ad vsyn c_pa2 9_pad csi_d 4_pb1 4_pad csi_d 6_ua rt5_ txd_ pb18 _pad ssi4_ fs_p c16_ pa d ssi1_ fs_p c20_ pa d ssi2_ txda t_gp t4_t out_ pc26 _pad kp_r ow0_ pa d i2c_d ata _ p d17_ pa d kp_c ol1_ pa d kp_c ol5_ pa d uart 3_rx d_pe 9_pa d uart 1_rx d_pe 13_pa d tck_p ad cspi1 _sclk _pd29 _pad usbh 1_txd m_ua rt4_t xd_p b28 cspi 2_ss 0_us bh2_ data 6_pd 21 usb _pw r_p b23_ pa d i2c2 _sc l_p c6_ pa d gld8_ pa 1 4 _pad ld6 _pa1 2_pa d ld17_ pa23_ pa d cls_ pa 2 5 _ pa d csi_v sync _uar t5_c ts_p b20_ pa d ssi4_ txda t_pc 18_pa d ssi2_ fs_g pt5_ tout _pc2 4_pa d nvdd 11 nvdd 10 qvdd qvdd nvdd 9 nvdd 8 qvdd sd1_c lk_cs pi3_s clk_p e23_p ad usbo tg_d ata 1 _ pc11_ pa d usbh 1_sus p_pb2 2_pad cspi 2_mi so_u sbh2 _dat a2_p d23 usb otg _dat a2_ pc1 0_pa d usb otg _dat a6_ pc8 _pa d hnfrb _etm trac epkt 3_pf 0 ld4 _pa1 0_pa d ld12 _pa1 8_pa d ld13_ pa19_ pa d ld15_ pa 2 1 _ pa d nvdd 15 nvdd 14 usbo tg_d ata 5 _ pc7_p ad usb_ oc_b _pb2 4_pa d usbh 1_rc v_pb 25_p ad usb h2_ clk _pa0 _pa d usb otg _dat a4_ pc1 2_pa d jnfw p_b_ etmt rac epkt 1_pf 2 ld0 _pa6 _pa d ld2_ pa 8 _ pa d ld7_p a13_p ad ld5_p a11_p ad ld11_ pa17_ pa d upllv dd_pa d usbo tg_d ata 0 _ pc9_p ad usb h1_r xdm _pb3 0_pa d i2c2_ sda_ pc5_ pa d usb h2_ stp _pa4 _pa d usb h2_ data 7_pa 2_pa d table 59. i.mx27 full 17 17 mm package mapbga pin assignment (continued) 1 2 3 4 5 6 7 8 9 10111213141516 17 18 192021222324
i.mx27/i.mx27l block guide, rev. 1.3 108 freescale semiconductor package information and pinout knfal e_et mpip esta t0_p f4 lsc lk_ pa 5 _ pa d ld3_p a9_pa d ld1_p a7_pa d ld9_ pa15_ pa d gnd gnd gnd gnd gnd gnd rtcv ss_pa d rtcv dd_pa d usb otg_ data 3_pc 13_p ad usb h2_ dir_ pa 1 _ pa d usb otg _cl k_p e24_ pa d lnfw e_b_ etm pipe stat 2_pf 6 nfc e_b _et mtr ace pkt 2_p f3 nfre _b_et mpip estat 1_pf5 nfcl e_et mtra cepk t0_pf 1 nvdd 12 gnd gnd gnd gnd gnd gnd nvdd 7 nvdd 7 usbh 2_nxt _pa3_ pa d usbo tg_s tp_k p_ro w6a_ pe1_ pa d osc 32k_ byp ass _pa d m d14_ pa d d15 _pa d d11_ pa d d13_p ad d9_pa d nvdd 1 gnd gnd gnd gnd gnd upll vss_ pa d fpmv dd_pa d nvdd 13 usb otg_ nxt_ kp_c ol6a _pe0 _pad usbo tg_d ata 7 _ pe25 _pad osc 32v dd_ pa d ext al32 k_pa d n d12_ pa d d7_ pa d d5_p ad d3_pa d d1_pa d nvdd 1 gnd gnd gnd gnd gnd gnd nvdd 6 powe r_on _res et_pa d usb otg_ dir_ kp_r ow7 a_pe 2_pa d pow er_c ut_p ad osc 32v ss_ pa d xtal 32k_ pa d p d10_ pa d d8_ pa d a9_pa d a12_p ad qvdd gnd gnd gnd gnd gnd fpmv ss_p ad nvdd 6 ata _ d ata 6 _ fec_ mdio_ pd8_p ad ata _ data 2_sd 3_d2 _pd4 _pad sd3 _cm d_p d0_ pa d sd3 _cl k_e tmt rac epk t15_ pd1 rd6_p ad d4_ pa d a5_pa d a7_pa d nvdd 2 gnd gnd gnd gnd gnd mpll vss_ pa d fuse vdd_ pa d fuse vss_p ad ata _ data 10_e tmt rac epkt 9_pd 12 ata _ data 0_s d3_ d0_ pd2 _pa d ata _ data 1_s d3_ d1_ pd3 _pa d table 59. i.mx27 full 17 17 mm package mapbga pin assignment (continued) 1 2 3 4 5 6 7 8 9 10111213141516 17 18 192021222324
i.mx27/i.mx27l block guide, rev. 1.3 freescale semiconductor 109 package information and pinout td2_p ad d0_ pa d ma10 _pad sdba 1_pad a1_pa d nvdd 2 mpllv dd_pa d avs s_ pa d ata _ data 14_e tmt rac epkt 5_pd 16 ata _ data 4_et mtra cepk t14_ pd6 ata _ data 5_et mtr ace pkt 13_p d7 ata _ data 3_s d3_ d3_ pd5 _pa d u a13_ pa d a11_ pa d a3_p ad sd31_ pa d a25_p ad nvdd 2 avdd _pad boot 2_pad iois1 6_at a_in trq_ pf9_ pa d ata _ data 8_et mtra cepk t11_ pd10 ata _ data 12_e tmt rac epk t7_p d14 ata _ data 7_et mtr ace pkt 12_p d9 va8_p ad a6_ pa d sd26_ pa d sd28_ pa d sd29 _pad a19_ pa d nvdd 2 nvdd 2 nvdd 3 nvdd 3 nvdd 4 qvdd qvdd qvdd nvdd 5 nvdd 5 osc2 6m_te st_pa d pc_p oe_a ta _ b uffe r_en _pf7 _pad boo t0_p ad ata _ data 9_et mtr ace pkt 10_p d11 wa4_p ad a2_ pa d sd23_ pa d sdqs 2_pad sd25 _pad sdqs 1_pa d sd13 _pad sd6_ pa d a16_ pa d dqm1 _pad sdwe _b_p ad cs3_ b_pa d cs5_ b_et mtra cecl k_pf 22_pa d eb0_ b_pa d ext_6 0m_pa d pc_c d1_b_ ata _ d ior_p f20_p ad pc_v s2_at a_da0 _pf13 _pad pc_b vd2_ ata _ dma ck_p f11_ pa d ata _ data 11_e tmt rac epk t8_p d13 ata _ data 13_e tmt rac epk t6_p d15 ya0_p ad sdb a0_ pa d sdq s3_p ad a20_p ad sd18 _pad sd15 _pad sd12 _pad sd8_ pa d a15_ pa d sd2_ pa d dqm2 _pad sdck e1_p ad cs2_ b_pa d lba_ b_pa d oe_b_ pa d pc_w ait_b _ata_ cs1_p f18_p ad pc_p wron _ata_ da2_p f16_p ad boot 3_pa d boo t1_p ad ata _ data 15_e tmt rac epk t4_p f23 table 59. i.mx27 full 17 17 mm package mapbga pin assignment (continued) 1 2 3 4 5 6 7 8 9 10111213141516 17 18 192021222324
i.mx27/i.mx27l block guide, rev. 1.3 110 freescale semiconductor package information and pinout aa sd30 _pad a24_ pa d sd27 _pad res et_ out _b_ pe1 7_pa d osc 26v dd_ pa d xtal 26m_ pa d ab a23_ pa d sd2 4_pa d a21_p ad sd21_ pa d sd10 _pad a14_ pa d sd0_ pa d ras_ b_pa d cs1_ b_pa d bclk_ pa d clk mod e0_p ad clkm ode1 _pad osc 26v ss_ pa d exta l26m _pad ac gnd gnd a22_ pa d sd20_ pa d sd17_ pa d a18_p ad a17_ pa d sd9_ pa d sd5_ pa d sd4_ pa d sd1_ pa d a10_ pa d cas_ b_pa d sdck e0_p ad rw_b _pad ecb_ b_pa d eb1_b _pad jtag_ ctrl_ pa d pc_c d2_b_ ata _ d iow_p f19_p ad pc_v s1_a ta_d a1_p f14_ pa d pc_r st_a ta _ r eset _b_p f10_ pa d res et_i n_b _pa d gnd gnd ad gnd gnd sd22 _pad sd19_ pa d sd16_ pa d sd14_ pa d sd11 _pad sd7_ pa d sdqs 0_pa d sd3_ pa d dqm3 _pad dqm0 _pad sdcl k_pa d sdcl k_pa d_b cs4_ b_et mtra cesy nc_p f21_p ad cs0_ b_pa d clko_ pf15_ pa d ext_2 66m_p ad pc_r eady_ ata _ c s0_pf 17_pa d pc_b vd1_ ata _ dma rq_p f12_ pa d pc_r w_b_ ata _ i ordy _pf8 _pad por _b_ pa d gnd gnd table 59. i.mx27 full 17 17 mm package mapbga pin assignment (continued) 1 2 3 4 5 6 7 8 9 10111213141516 17 18 192021222324
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 111 package information and pinout table 60 shows the device pin list, sorted by signal iden tification, including pad locations for ground and power supply voltages. table 60. i.mx27 24 mm 24 mm bga (17 mm 17 mm)?signal id by ball grid location pin name ball grid location a0 y1 a1 t6 a10 ac12 a11 u2 a12 p6 a13 u1 a14 ab9 a15 y11 a16 w11 a17 ac7 a18 ac6 a19 v8 a2 w2 a20 y6 a21 ab4 a22 ac3 a23 ab1 a24 aa2 a25 u6 a3 u3 a4 w1 a5 r5 a6 v2 a7 r6 a8 v1 a9 p5 ata_data0_sd3_d0_pd2 r23 ata_data1_sd3_d1_pd3 r24 ata_data10_etmtracepkt9_pd12 r20 ata_data11_etmtracepkt8_pd13 w23 ata_data12_etmtracepkt7_pd14 u23
i.mx27 and i.mx27l data sheet, rev. 1.3 112 freescale semiconductor package information and pinout ata_data13_etmtracepkt6_pd15 w24 ata_data14_etmtracepkt5_pd16 t20 ata_data15_etmtracepkt4_pf23 y24 ata_data2_sd3_d2_pd4 p20 ata_data3_sd3_d3_pd5 t24 ata_data4_etmtracepkt14_pd6 t22 ata_data5_etmtracepkt13_pd7 t23 ata_data6_fec_mdio_pd8 p19 ata_data7_etmtracepkt12_pd9 u24 ata_data8_etmtracepkt11_pd10 u22 ata_data9_etmtracepkt10_pd11 v24 a vdd u18 avss t19 bclk ab17 boot0 v23 boot1 y23 boot2 u19 boot3 y22 cas ac13 clkmode0 ab20 clkmode1 ab21 clko_pf15 ad17 cls_pa25 g6 contrast_pa30 c2 cs0 ad16 cs1 ab16 cs2 y15 cs3 w14 cs4 _etmtracesync_pf21 ad15 cs5 _etmtraceclk_pf22 w15 csi_d0_uart6_txd_pb10 c4 csi_d1_uart6_rxd_pb11 b4 csi_d2_uart6_cts_pb12 e6 table 60. i.mx27 24 mm 24 mm bga (17 mm 17 mm)?signal id by ball grid location (continued) pin name ball grid location
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 113 package information and pinout csi_d3_uart6_rts_pb13 a5 csi_d4_pb14 f6 csi_d5_pb17 a6 csi_d6_uart5_txd_pb18 f7 csi_d7_uart5_rxd_pb19 b6 csi_hsync_uart5_rts_pb21 a7 csi_mclk_pb15 b5 csi_pixclk_pb16 e7 csi_vsync_uart5_cts_pb20 g7 cspi1_miso_pd30 a22 cspi1_mosi_pd31 c21 cspi1_rdy_pd25 b21 cspi1_sclk_pd29 f18 cspi1_ss0_pd28 b22 cspi1_ss1_pd27 c20 cspi1_ss2_usbh2_data5_pd26 e22 cspi2_miso_usbh2_data2_pd23 g20 cspi2_mosi_usbh2_data1_pd24 e23 cspi2_sclk_usbh2_data0_pd22 d23 cspi2_ss0_usbh2_data6_pd21 f20 cspi2_ss1_usbh2_data3_pd20 c23 cspi2_ss2_usbh2_data4_pd19 d22 d0 t2 d1 n6 d2 t1 d3 n5 d4 r2 d5 n3 d6 r1 d7 n2 d8 p2 d9 m6 d10 p1 table 60. i.mx27 24 mm 24 mm bga (17 mm 17 mm)?signal id by ball grid location (continued) pin name ball grid location
i.mx27 and i.mx27l data sheet, rev. 1.3 114 freescale semiconductor package information and pinout d11 m3 d12 n1 d13 m5 d14 m1 d15 m2 dqm0 ad12 dqm1 w12 dqm2 y13 dqm3 ad11 eb0 w16 eb1 ac17 ecb ac16 ext_266m ad18 ext_60m w17 extal26m ab24 extal32k m24 fpm vdd m18 fpmvss p15 fuse vdd r18 fusevss r19 gnd l12 gnd n10 gnd n11 gnd n12 gnd n13 gnd n14 gnd n15 gnd p10 gnd p11 gnd p12 gnd p13 gnd p14 gnd r10 table 60. i.mx27 24 mm 24 mm bga (17 mm 17 mm)?signal id by ball grid location (continued) pin name ball grid location
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 115 package information and pinout gnd r11 gnd r12 gnd r13 gnd r14 hsync_pa28 d1 i2c_clk_pd18 b13 i2c_data_pd17 f12 i2c2_scl_pc6 f24 i2c2_sda_pc5 j22 iois16_ata_intrq_pf9 u20 jtag_ctrl ac18 kp_col0 b14 kp_col1 f13 kp_col2 a15 kp_col3 e13 kp_col4 b15 kp_col5 f14 kp_row0 f11 kp_row1 a12 kp_row2 c12 kp_row3 b12 kp_row4 e11 kp_row5 a13 lba y16 ld0_pa6 j2 ld1_pa7 k6 ld10_pa16 f2 ld11_pa17 j7 ld12_pa18 h3 ld13_pa19 h5 ld14_pa20 f1 ld15_pa21 h6 ld16_pa22 e2 table 60. i.mx27 24 mm 24 mm bga (17 mm 17 mm)?signal id by ball grid location (continued) pin name ball grid location
i.mx27 and i.mx27l data sheet, rev. 1.3 116 freescale semiconductor package information and pinout ld17_pa23 g5 ld2_pa8 j3 ld3_pa9 k5 ld4_pa10 h2 ld5_pa11 j6 ld6_pa12 g2 ld7_pa13 j5 ld8_pa14 g1 ld9_pa15 k7 lsclk_pa5 k2 ma10 t3 mpll vdd t18 mpllvss r15 n vdd 2v10 nfale_etmpipestat0_pf4 k1 nfce_b_etmtracepkt2_pf3 l2 nfcle_etmtracepkt0_pf1 l6 frb_etmtracepkt3_pf0 h1 nfre _etmpipestat1_pf5 l5 nfwe _etmpipestat2_pf6 l1 nfwp _etmtracepkt1_pf2 j1 n vdd 1m7 n vdd 1n7 n vdd 10 g11 n vdd 11 g10 n vdd 12 l7 n vdd 13 m19 n vdd 14 h18 n vdd 15 h7 n vdd 2r7 n vdd 2t7 n vdd 2u7 n vdd 2v9 table 60. i.mx27 24 mm 24 mm bga (17 mm 17 mm)?signal id by ball grid location (continued) pin name ball grid location
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 117 package information and pinout n vdd 3v11 n vdd 3v12 n vdd 4v13 n vdd 5v17 n vdd 5v18 n vdd 6n18 n vdd 6p18 n vdd 7l18 n vdd 7l19 n vdd 8g15 n vdd 9g14 gnd a1 gnd a24 gnd ac1 gnd ac2 gnd a23 gnd ac23 gnd a2 gnd ac24 gnd ad1 gnd ad2 gnd ad23 gnd ad24 gnd b1 gnd b2 gnd b23 gnd b24 gnd k10 gnd k11 gnd k12 gnd k13 gnd k14 gnd k15 table 60. i.mx27 24 mm 24 mm bga (17 mm 17 mm)?signal id by ball grid location (continued) pin name ball grid location
i.mx27 and i.mx27l data sheet, rev. 1.3 118 freescale semiconductor package information and pinout gnd l10 gnd l11 oe y17 oe_acd_pa31 d3 osc26m_test v19 osc26 vdd aa23 osc26vss ab23 osc32k_bypass l24 osc32 vdd m23 osc32vss n23 pc_bvd1_ata_dmarq_pf12 ad20 pc_bvd2_ata_dmack_pf11 w20 pc_cd1_b_ata_dior_pf20 w18 pc_cd2_b_ata_diow_pf19 ac19 pc_poe_ata_buffer_en_pf7 v20 pc_pwron_ata_da2_pf16 y19 pc_ready_ata_cs0_pf17 ad19 pc_rst_ata_reset _pf10 ac21 pc_rw _ata_iordy_pf8 ad21 pc_vs1_ata_da1_pf14 ac20 pc_vs2_ata_da0_pf13 w19 pc_wait _ata_cs1_pf18 y18 por ad22 power_cut n22 power_on_reset n19 ps_pa26 d2 pwmo_pe5 c13 q vdd g12 q vdd g13 q vdd g16 q vdd p7 q vdd v14 q vdd v15 table 60. i.mx27 24 mm 24 mm bga (17 mm 17 mm)?signal id by ball grid location (continued) pin name ball grid location
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 119 package information and pinout q vdd v16 qvss l13 qvss l14 qvss l15 qvss m10 qvss m11 qvss m12 qvss m13 qvss m14 ras ab13 reset_in ac22 reset_out _pe17 aa22 rev_pa24 e1 rtck_owire_pe16 a19 rtc vdd k19 rtcvss k18 rw_b ac15 sd0 ab12 sd1 ac11 sd1_clk_cspi3_sclk_pe23 g17 sd1_cmd_cspi3_mosi_pe22 a21 sd1_d0_cspi3_miso_pe18 a20 sd1_d1_pe19 e17 sd1_d2_pe20 b20 sd1_d3_cspi3_ss_pe21 e18 sd10 ab8 sd11 ad7 sd12 y9 sd13 w9 sd14 ad6 sd15 y8 sd16 ad5 sd17 ac5 table 60. i.mx27 24 mm 24 mm bga (17 mm 17 mm)?signal id by ball grid location (continued) pin name ball grid location
i.mx27 and i.mx27l data sheet, rev. 1.3 120 freescale semiconductor package information and pinout sd18 y7 sd19 ad4 sd2 y12 sd2_clk_mshc_sclk_pb9 a4 sd2_cmd_mshc_bs_pb8 c5 sd2_d0_mshc_data0_pb4 c1 sd2_d1_mshc_data1_pb5 e3 sd2_d2_mshc_data2_pb6 c8 sd2_d3_mshc_data3_pb7 a3 sd20 ac4 sd21 ab5 sd22 ad3 sd23 w5 sd24 ab2 sd25 w7 sd26 v5 sd27 aa3 sd28 v6 sd29 v7 sd3 ad10 sd3_clk_etmtracepkt15_pd1 p24 sd3_cmd_pd0_ p23 sd30 aa1 sd31 u5 sd4 ac10 sd5 ac9 sd6 w10 sd7 ad8 sd8 y10 sd9 ac8 sdba0 y2 sdba1 t5 sdcke0 ac14 table 60. i.mx27 24 mm 24 mm bga (17 mm 17 mm)?signal id by ball grid location (continued) pin name ball grid location
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 121 package information and pinout sdcke1 y14 sdclk ad13 sdclk ad14 sdqs0 ad9 sdqs1 w8 sdqs2 w6 sdqs3 y3 sdwe w13 spl_spr_pa27 b3 ssi1_clk_pc23 b9 ssi1_fs_pc20 f9 ssi1_rxdat_pc21 a9 ssi1_txdat_pc22 e9 ssi2_clk_gpt4_tin_pc27 b10 ssi2_fs_gpt5_tout_pc24 g9 ssi2_rxdat_gpt5_tin_pc25 a10 ssi2_txdat_gpt4_tout_pc26 f10 ssi3_clk_slcdc2_clk_pc31 b11 ssi3_fs_slcdc2_d0_pc28 e10 ssi3_rxdat_slcdc2_rs_pc29 a11 ssi3_txdat_slcdc2_cs_pc30 c9 ssi4_clk_pc19 b8 ssi4_fs_pc16 f8 ssi4_rxdat_pc17 a8 ssi4_txdat_pc18 g8 tck f17 tdi b18 tdo e16 tin_pc15 b7 tms b19 tout_pc14 e8 trst c17 uart1_cts_pe14 a18 table 60. i.mx27 24 mm 24 mm bga (17 mm 17 mm)?signal id by ball grid location (continued) pin name ball grid location
i.mx27 and i.mx27l data sheet, rev. 1.3 122 freescale semiconductor package information and pinout uart1_rts_pe15 c16 uart1_rxd_pe13 f16 uart1_txd_pe12 b17 uart2_cts_kp_col7_pe3_pad e12 uart2_rts_kp_row7_pe4 a14 uart2_rxd_kp_row6_pe7 e14 uart2_txd_kp_col6_pe6 a16 uart3_cts_pe10 a17 uart3_rts_pe11 e15 uart3_rxd_pe9 f15 uart3_txd_pe8 b16 upll vdd j18 upllvss m15 usb_oc _pb24 h20 usb_pwr_pb23 f23 usbh1_fs_uart4_rts_pb26 e19 usbh1_oe _pb27 c24 usbh1_rcv_pb25 h22 usbh1_rxdm_pb30 j20 usbh1_rxdp_uart4_rxd_pb31 e24 usbh1_susp_pb22 g19 usbh1_txdm_uart4_txd_pb28 f19 usbh1_txdp_uart4_cts_pb29 d24 usbh2_clk_pa0 h23 usbh2_data7_pa2_suspend j24 usbh2_dir_pa1 k23 usbh2_nxt_pa3 l20 usbh2_stp_pa4 j23 usbotg_clk_pe24 k24 usbotg_data0_pc9_oen j19 usbotg_data1_pc11_txdp g18 usbotg_data2_pc10_txdm g23 usbotg_data3_pc13_rxdp k20 table 60. i.mx27 24 mm 24 mm bga (17 mm 17 mm)?signal id by ball grid location (continued) pin name ball grid location
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 123 package information and pinout usbotg_data4_pc12_rxdm h24 usbotg_data5_pc7_rcv h19 usbotg_data6_pc8_speed g24 usbotg_data7_pe25_suspend m22 usbotg_dir_kp_row7a_pe2 n20 usbotg_nxt_kp_col6a_pe0 m20 usbotg_stp_kp_row6a_pe1 l23 vsync_pa29 f5 xtal26m aa24 xtal32k n24 notes: 1. gnd and qvss contacts are tied together inside the bga package 2. freescale recommends tying gnd and qvss contacts to a single plane. table 60. i.mx27 24 mm 24 mm bga (17 mm 17 mm)?signal id by ball grid location (continued) pin name ball grid location
i.mx27 and i.mx27l data sheet, rev. 1.3 124 freescale semiconductor package information and pinout 5.3 full package outline drawing (19 mm 19 mm) figure 69 shows the package drawings and dimensions of the production package. figure 69. i.mx27/mx27l 19 19 mm full package mapbga: mechanical drawing
i.mx27/i.mx27l block guide, rev. 1.3 freescale semiconductor 125 package information and pinout 5.4 pin assignments (19 mm 19 mm) table 61 shows the i.mx27 full 19 19 mm package mapbga pin assignment. table 62 identifies the pin assignments for the ball grid array (bga) for full package. the connections of these pins depend solely upon the user application, however there are a few factory test signals that are not used in a normal application. following is a list of these signals and how they are to be terminated for proper operation of the i.mx27/mx27l processor: ? clkmode[1:0]: to ensure proper operation, leave these signals as no connects. ? osc26m_test: to ensure proper operation, leave this signal as no connect. ? ext_60m: to ensure proper operation, connect this signal to ground. ? ext_266m: to ensure proper operation, connect this signal to ground. ? most of the signals shown in table 62 are multiplexed with other signals. for ease of reference, all of the signals at a particular pad are shown in the form of a compound signal name. refer to table 3 for complete information on the signal multiplexing schemes of these signals. table 61. i.mx27 full 19 mm 19 mm package mapbga pin assignment 1234567891011121314151617181920212223 a gnd gnd sd2_ d3_m shc_ data3 _pb7_ pa d csi_d 1_uar t6_rx d_pb1 1_pad csi_m clk_p b15_p ad csi_d 5_pb1 7_pad tout _pc14 _pad ssi4_ clk_p c19_p ad ssi1_ clk_p c23_p ad ssi3_ fs_sl cdc2 _d0_p c28_p ad ssi3_ clk_s lcdc 2_clk _pc31 _pad kp_r ow3_ pa d uart 2_ct s_kp _col 7_pe 3_pa d pwm o_pe 5_pa d kp_c ol4_ pa d uart3 _txd_ pe8_p ad uart 1_rx d_pe 13_p ad rtck _owi re_p e16_ pa d sd1_ d1_p e19_ pa d sd1_ cmd _cs pi3_ mosi _pe2 2_pa d cspi 1_mi so_ pd30 _pad gnd gnd b gnd gnd sd2_ d1_m shc_ data1 _pb5_ pa d sd2_ cmd_ mshc _bs_p b8_pa d csi_d 2_uar t6_ct s_pb1 2_pad csi_pi xclk_ pb16_ pa d csi_h sync _uart 5_rts _pb21 _pad ssi4_ rxda t_pc1 7_pad ssi1_ txdat _pc22 _pad ssi2_ rxda t_gp t5_ti n_pc 25_pa d ssi3_ rxda t_slc dc2_ rs_p c29_p ad kp_r ow2_ pa d i2c_c lk_p d18_ pa d kp_c ol2_ pa d kp_c ol5_ pa d uart3 _cts_ pe10_ pa d uart 1_ct s_pe 14_p ad sd1_ d0_c spi3_ miso _pe1 8_pa d sd1_ d2_p e20_ pa d cspi 1_rd y_p d25_ pa d cspi 1_ss 0_pd 28_p ad gnd gnd c sd2_ d0_m shc_ data0 _pb4_ pa d cont rast _pa30 _pad oe_a cd_pa 31_pa d sd2_ d2_m shc_ data2 _pb6_ pa d csi_d 0_uar t6_tx d_pb1 0_pad csi_d 4_pb1 4_pad csi_d 7_uar t5_rx d_pb1 9_pad tin_p c15_p ad ssi1_ fs_p c20_p ad ssi2_ fs_g pt5_t out_ pc24_ pa d ssi3_ txdat _slc dc2_ cs_p c30_p ad kp_r ow4_ pa d uart 2_rt s_kp _row 7_pe 4_pa d kp_c ol3_ pa d uart 2_rx d_kp _row 6_pe 7_pa d uart3 _rts_ pe11_ pa d uart 1_rt s_pe 15_p ad tms_ pa d sd1_ clk_ cspi 3_sc lk_p e23_ pa d cspi 1_m osi_ pd31 _pad cspi 1_ss 1_pd 27_p ad cspi 2_ss 1_us bh2_ data 3_pd 20 cspi 2_ss 0_us bh2_ data 6_pd 21
i.mx27/i.mx27l block guide, rev. 1.3 126 freescale semiconductor package information and pinout d hsyn c_pa2 8_pad ps_pa 26_pa d spl_s pr_pa 27_pa d vsyn c_pa2 9_pad sd2_ clk_ mshc _sclk _pb9_ pa d csi_d 3_uar t6_rt s_pb1 3_pad csi_d 6_uar t5_tx d_pb1 8_pad ssi4_ fs_p c16_p ad ssi1_ rxda t_pc2 1_pad ssi2_ clk_ gpt4_ tin_p c27_p ad kp_r ow1_ pa d kp_r ow5_ pa d kp_c ol0_ pa d uart 2_tx d_kp _col 6_pe 6_pa d uart 1_tx d_pe 12_pa d tdo_ pa d tdi_ pa d sd1_ d3_c spi3_ ss_p e21_ pa d cspi 1_sc lk_p d29_ pa d cspi 1_ss 2_us bh2_ data 5_pd 26 cspi 2_ss 2_us bh2_ data 4_pd 19 cspi 2_sc lk_u sbh2 _dat a0_p d22 cspi 2_mo si_u sbh2 _dat a1_p d24 e ld15_ pa 2 1 _ pa d ld16_ pa 2 2 _ pa d ld17_ pa23_ pa d cls_p a25_p ad cspi 2_mi so_ usb h2_d ata 2 _pd2 3 usb _pw r_p b23_ pa d usb_ oc_b _pb2 4_pa d usb h1_r cv_p b25_ pa d f ld13_ pa 1 9 _ pa d ld12_ pa 1 8 _ pa d ld14_ pa20_ pa d rev_ pa 2 4 _ pa d gnd gnd csi_v sync _uart 5_cts _pb20 _pad ssi4_ txdat _pc18 _pad ssi2_ txdat _gpt4 _tou t_pc2 6_pad kp_r ow0_ pa d i2c_d ata _ p d17_ pa d kp_c ol1_ pa d uart 3_rx d_pe 9_pa d tck_ pa d trst_ b_pad qvd d gnd usb h1_f s_ua rt4_ rts_ pb26 _pad usb h1_ oe_ b_pb 27_p ad usb h1_t xdm _uar t4_t xd_p b28 usb h1_t xdp_ uart 4_ct s_pb 29 g ld8_p a14_p ad ld7_p a13_p ad ld10_ pa16_ pa d ld11_ pa 1 7 _ pa d nvdd 15 gnd nvdd 11 nvdd 11 nvdd 11 nvdd 10 nvdd 10 nvdd 9 nvdd 9 nvdd 8 nvdd 8 qvd d usbh 1_su sp_p b22_ pa d usb h1_r xdm _pb3 0_pa d usb h1_r xdp _ua rt4_ rxd _pb3 1 i2c2_ sda_ pc5_ pa d i2c2_ scl_ pc6_ pa d h ld3_p a9_pa d ld5_p a11_p ad ld6_p a12_p ad ld9_p a15_p ad nvdd 15 qvdd qvdd qvdd qvdd qvdd qvdd qvdd qvdd qvdd qvdd qvd d nvd d14 usb otg _dat a5_p c7_p ad usb otg _dat a6_p c8_p ad usb otg_ data 0_pc 9_pa d usb otg_ data 2_pc 10_p ad j ld0_p a6_pa d ld1_p a7_pa d ld2_p a8_pa d ld4_p a10_p ad nvdd 12 nvdd 12 qvdd gnd gnd gnd gnd gnd gnd gnd qvdd nvd d14 nvd d7 usb otg _dat a1_p c11_ pa d usb otg _dat a4_p c12_ pa d usb otg_ data 3_pc 13_p ad usb h2_c lk_p a0_p ad table 61. i.mx27 full 19 mm 19 mm package mapbga pin assignment (continued) 1234567891011121314151617181920212223
i.mx27/i.mx27l block guide, rev. 1.3 freescale semiconductor 127 package information and pinout k nfwp _b_et mtra cepk t1_pf 2 nfrb _etm trac epkt3 _pf0 nfce _b_et mtra cepk t2_pf 3 lsclk _pa5_ pa d nvdd 1 nvdd 1 qvdd gnd gnd gnd gnd gnd gnd gnd qvdd upll vdd_ pa d nvd d7 usb h2_d ir_p a1_p ad usb h2_d ata 7 _pa2 _pad usb h2_n xt_p a3_p ad usb h2_s tp_p a4_p ad l nfwe _b_et mpipe stat2 _pf6 nfale _etm pipes tat 0 _ pf4 nfre _b_et mpipe stat1 _pf5 nfcl e_et mtra cepk t0_pf 1 nvdd 1 nvdd 1 qvdd gnd gnd gnd gnd gnd gnd gnd qvdd upll vss_ pa d nvd d13 usb otg _dat a7_p e25_ pa d usb otg _nxt _kp_ col 6a_p e0_p ad usb otg_ clk_ pe24 _pad usb otg_ stp_ kp_r ow6 a_pe 1_pa d m d15_p ad d14_p ad d12_p ad d13_p ad d11_p ad qvdd qvdd gnd gnd gnd gnd gnd gnd gnd qvdd rtcv ss_p ad rtcv dd_p ad usb otg _dir _kp_ row 7a_p e2_p ad osc 32k_ bypa ss_p ad pow er_o n_re set_ pa d pow er_c ut_p ad n d10_p ad d9_pa d d5_pa d d8_pa d d7_pa d d0_pa d qvdd gnd gnd gnd gnd gnd gnd gnd qvdd fpmv ss_p ad fpmv dd_p ad sd3_ cmd _pd0 _pad osc 32vd d_pa d osc3 2vss _pad exta l32k _pad p d6_pa d d4_pa d d3_pa d nc_p 4_1 ma10_ pa d nvdd 2 qvdd gnd gnd gnd gnd gnd gnd gnd qvdd nvd d6 nvd d6 ata _ data 0_sd 3_d0 _pd2 _pad ata _ data 1_sd 3_d1 _pd3 _pad sd3_ clk_ etmt race pkt1 5_pd 1 xtal 32k_ pa d r d2_pa d d1_pa d a13_p ad a12_p ad nvdd 2 nvdd 2 qvdd gnd gnd gnd gnd gnd gnd gnd qvdd fuse vss_ pa d fuse vdd_ pa d ata _ data 5_et mtr ace pkt1 3_pd 7 ata _ data 4_et mtr ace pkt1 4_pd 6 ata _ data 3_sd 3_d3 _pd5 _pad ata _ data 2_sd 3_d2 _pd4 _pad table 61. i.mx27 full 19 mm 19 mm package mapbga pin assignment (continued) 1234567891011121314151617181920212223
i.mx27/i.mx27l block guide, rev. 1.3 128 freescale semiconductor package information and pinout t a11_p ad a9_pa d a8_pa d a7_pa d a1_pa d nvdd 2 qvdd qvdd qvdd qvdd qvdd qvdd qvdd qvdd qvdd mpll vss_ pa d boot 2_pa d ata _ data 8_et mtr ace pkt1 1_pd 10 ata _ data 9_et mtr ace pkt1 0_pd 11 ata _ data 7_et mtr acep kt12 _pd9 ata _ data 6_fe c_m dio_ pd8_ pa d u a6_pa d a5_pa d a4_pa d a3_pa d sd29_ pa d nvdd 2 nvdd 2 nvdd 2 qvdd nvdd 3 nvdd 3 sdck e1_p ad nvdd 4 nvdd 4 nvdd 4 av dd _pad av ss _pad ata _ data 13_e tmt rac epk t6_p d15 ata _ data 12_e tmt rac epk t7_p d14 ata _ data 11_e tmt race pkt8 _pd1 3 ata _ data 10_e tmt race pkt9 _pd1 2 v a2_pa d a0_pa d sdba 0_pad sd31_ pa d a22_p ad gnd gnd sd12_ pa d sd6_p ad sd2_p ad dqm1 _pad sdck e0_p ad cs5_ b_et mtra cecl k_pf 22_pa d nvdd 5 nvdd 5 mpll vdd_ pa d gnd boo t1_p ad boo t0_p ad ata _ data 15_e tmt race pkt4 _pf2 3 ata _ data 14_e tmt race pkt5 _pd1 6 w sdba 1_pad a25_p ad sdqs 3_pad sd27_ pa d osc 26m_ test _pad osc 26vs s_pa d osc2 6vdd _pad boo t3_p ad y sd30_ pa d a24_p ad sd28_ pa d sd26_ pa d sd20_ pa d sd17_ pa d a19_p ad sd13_ pa d sd9_p ad sdqs 0_pad dqm3 _pad ras_ b_pa d sdcl k_pa d_b cs4_ b_et mtra cesy nc_p f21_p ad cs0_ b_pa d oe_b_ pa d pc_c d2_b _ata_ diow _pf1 9_pa d pc_v s1_a ta _ d a1_p f14_ pa d pc_r st_a ta _ r eset _b_p f10_ pa d pc_ poe _ata _buf fer_ en_ pf7_ pa d por _b_p ad clk mod e1_p ad exta l26m _pad aa sd25_ pa d a23_p ad sd24_ pa d sd22_ pa d a20_p ad sd16_ pa d sd15_ pa d sd11_ pa d sd7_p ad a15_p ad sd0_p ad dqm0 _pad sdcl k_pa d rw_b _pad cs1_ b_pa d eb0_b _pad ext_ 60m_ pa d pc_ wait _b_a ta _ c s1_p f18_ pa d pc_b vd1_ ata _ dma rq_p f12_ pa d iois1 6_at a_in trq _pf9 _pad res et_i n_b_ pa d clk mod e0_p ad xtal 26m_ pa d table 61. i.mx27 full 19 mm 19 mm package mapbga pin assignment (continued) 1234567891011121314151617181920212223
i.mx27/i.mx27l block guide, rev. 1.3 freescale semiconductor 129 package information and pinout ab gnd gnd sdqs 2_pad sd21_ pa d sd19_ pa d sdqs 1_pad sd14_ pa d sd10_ pa d sd5_p ad sd4_p ad sd1_p ad a10_ pa d sdwe _b_p ad cs2_ b_pa d ecb_ b_pa d eb1_b _pad jtag _ctr l_pa d pc_c d1_b _ata_ dior _pf2 0_pa d pc_r eady _ata_ cs0_ pf17 _pad pc_ bvd 2_at a_d mac k_pf 11_p ad pc_ rw_ b_at a_io rdy_ pf8_ pa d gnd gnd ac gnd gnd sd23_ pa d a21_p ad sd18_ pa d a18_p ad a17_p ad sd8_p ad a16_p ad a14_p ad sd3_p ad dqm2 _pad cas_ b_pa d cs3_ b_pa d lba_ b_pa d bclk_ pa d clko _pf1 5_pa d ext_ 266m _pad pc_p wro n_at a_da 2_pf 16_p ad pc_ vs2_ ata _ da0_ pf13 _pad res et_ out _b_p e17_ pa d gnd gnd table 61. i.mx27 full 19 mm 19 mm package mapbga pin assignment (continued) 1234567891011121314151617181920212223
i.mx27 and i.mx27l data sheet, rev. 1.3 130 freescale semiconductor package information and pinout table 62 shows the device pin list, sorted by sorted by location. table 62. i.mx27 23 mm 23 mm bga (19 mm 19 mm)?signal id by ball grid location location contact name a1 gnd a2 gnd a3 sd2_d3_mshc_data3_pb7 a4 csi_d1_uart6_rxd_pb11 a5 csi_mclk_pb15 a6 csi_d5_pb17 a7 tout_pc14 a8 ssi4_clk_pc19 a9 ssi1_clk_pc23 a10 ssi3_fs_slcdc2_d0_pc28 a11 ssi3_clk_slcdc2_clk_pc31 a12 kp_row3 a13 uart2_cts_kp_col7_pe3 a14 pwmo_pe5 a15 kp_col4 a16 uart3_txd_pe8 a17 uart1_rxd_pe13 a18 rtck_owire_pe16 a19 sd1_d1_pe19 a20 sd1_cmd_cspi3_mosi_pe22 a21 cspi1_miso_pd30 a22 gnd a23 gnd aa1 sd25 aa2 a23 aa3 sd24 aa4 sd22 aa5 a20 aa6 sd16 aa7 sd15 aa8 sd11 aa9 sd7
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 131 package information and pinout aa10 a15 aa11 sd0 aa12 dqm0 aa13 sdclk aa14 rw_b aa15 cs1_b aa16 eb0_b aa17 ext_60m aa18 pc_wait_b_ata_cs1_pf18 aa19 pc_bvd1_ata_dmarq_pf12 aa20 iois16_ata_intrq_pf9 aa21 reset_in_b aa22 clkmode0 aa23 xtal26m ab1 gnd ab2 gnd ab3 sdqs2 ab4 sd21 ab5 sd19 ab6 sdqs1 ab7 sd14 ab8 sd10 ab9 sd5 ab10 sd4 ab11 sd1 ab12 a10 ab13 sdwe_b ab14 cs2_b ab15 ecb_b ab16 eb1_b ab17 jtag_ctrl ab18 pc_cd1_b_ata_dior_pf20 ab19 pc_ready_ata_cs0_pf17 table 62. i.mx27 23 mm 23 mm bga (19 mm 19 mm)?signal id by ball grid location (continued) location contact name
i.mx27 and i.mx27l data sheet, rev. 1.3 132 freescale semiconductor package information and pinout ab20 pc_bvd2_ata_dmack_pf11 ab21 pc_rw_b_ata_iordy_pf8 ab22 gnd ab23 gnd ac1 gnd ac2 gnd ac3 sd23 ac4 a21 ac5 sd18 ac6 a18 ac7 a17 ac8 sd8 ac9 a16 ac10 a14 ac11 sd3 ac12 dqm2 ac13 cas_b ac14 cs3_b ac15 lba_b ac16 bclk ac17 clko_pf15 ac18 ext_266m ac19 pc_pwron_ata_da2_pf16 ac20 pc_vs2_ata_da0_pf13 ac21 reset_out_b_pe17 ac22 gnd ac23 gnd b1 gnd b2 gnd b3 sd2_d1_mshc_data1_pb5 b4 sd2_cmd_mshc_bs_pb8 b5 csi_d2_uart6_cts_pb12 b6 csi_pixclk_pb16 table 62. i.mx27 23 mm 23 mm bga (19 mm 19 mm)?signal id by ball grid location (continued) location contact name
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 133 package information and pinout b7 csi_hsync_uart5_rts_pb21 b8 ssi4_rxdat_pc17 b9 ssi1_txdat_pc22 b10 ssi2_rxdat_gpt5_tin_pc25 b11 ssi3_rxdat_slcdc2_rs_pc29 b12 kp_row2 b13 i2c_clk_pd18 b14 kp_col2 b15 kp_col5 b16 uart3_cts_pe10 b17 uart1_cts_pe14 b18 sd1_d0_cspi3_miso_pe18 b19 sd1_d2_pe20 b20 cspi1_rdy_pd25 b21 cspi1_ss0_pd28 b22 gnd b23 gnd c1 sd2_d0_mshc_data0_pb4 c2 contrast_pa30 c3 oe_acd_pa31 c4 sd2_d2_mshc_data2_pb6 c5 csi_d0_uart6_txd_pb10 c6 csi_d4_pb14 c7 csi_d7_uart5_rxd_pb19 c8 tin_pc15 c9 ssi1_fs_pc20 c10 ssi2_fs_gpt5_tout_pc24 c11 ssi3_txdat_slcdc2_cs_pc30 c12 kp_row4 c13 uart2_rts_kp_row7_pe4 c14 kp_col3 c15 uart2_rxd_kp_row6_pe7 c16 uart3_rts_pe11 table 62. i.mx27 23 mm 23 mm bga (19 mm 19 mm)?signal id by ball grid location (continued) location contact name
i.mx27 and i.mx27l data sheet, rev. 1.3 134 freescale semiconductor package information and pinout c17 uart1_rts_pe15 c18 tms c19 sd1_clk_cspi3_sclk_pe23 c20 cspi1_mosi_pd31 c21 cspi1_ss1_pd27 c22 cspi2_ss1_usbh2_data3_pd20 c23 cspi2_ss0_usbh2_data6_pd21 d1 hsync_pa28 d2 ps_pa26 d3 spl_spr_pa27 d4 vsync_pa29 d5 sd2_clk_mshc_sclk_pb9 d6 csi_d3_uart6_rts_pb13 d7 csi_d6_uart5_txd_pb18 d8 ssi4_fs_pc16 d9 ssi1_rxdat_pc21 d10 ssi2_clk_gpt4_tin_pc27 d11 kp_row1 d12 kp_row5 d13 kp_col0 d14 uart2_txd_kp_col6_pe6 d15 uart1_txd_pe12 d16 tdo d17 tdi d18 sd1_d3_cspi3_ss_pe21 d19 cspi1_sclk_pd29 d20 cspi1_ss2_usbh2_data5_pd26 d21 cspi2_ss2_usbh2_data4_pd19 d22 cspi2_sclk_usbh2_data0_pd22 d23 cspi2_mosi_usbh2_data1_pd24 e1 ld15_pa21 e2 ld16_pa22 e3 ld17_pa23 table 62. i.mx27 23 mm 23 mm bga (19 mm 19 mm)?signal id by ball grid location (continued) location contact name
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 135 package information and pinout e4 cls_pa25 e20 cspi2_miso_usbh2_data2_pd23 e21 usb_pwr_pb23 e22 usb_oc_b_pb24 e23 usbh1_rcv_pb25 f1 ld13_pa19 f2 ld12_pa18 f3 ld14_pa20 f4 rev_pa24 f6 gnd f7 gnd f8 csi_vsync_uart5_cts_pb20 f9 ssi4_txdat_pc18 f10 ssi2_txdat_gpt4_tout_pc26 f11 kp_row0 f12 i2c_data_pd17 f13 kp_col1 f14 uart3_rxd_pe9 f15 tck f16 trst_b f17 qvdd f18 gnd f20 usbh1_fs_uart4_rts_pb26 f21 usbh1_oe_b_pb27 f22 usbh1_txdm_uart4_txd_pb28 f23 usbh1_txdp_uart4_cts_pb29 g1 ld8_pa14 g2 ld7_pa13 g3 ld10_pa16 g4 ld11_pa17 g6 nvdd15 g7 gnd g8 nvdd11 table 62. i.mx27 23 mm 23 mm bga (19 mm 19 mm)?signal id by ball grid location (continued) location contact name
i.mx27 and i.mx27l data sheet, rev. 1.3 136 freescale semiconductor package information and pinout g9 nvdd11 g10 nvdd11 g11 nvdd10 g12 nvdd10 g13 nvdd9 g14 nvdd9 g15 nvdd8 g16 nvdd8 g17 qvdd g18 usbh1_susp_pb22 g20 usbh1_rxdm_pb30 g21 usbh1_rxdp_uart4_rxd_pb31 g22 i2c2_sda_pc5 g23 i2c2_scl_pc6 h1 ld3_pa9 h2 ld5_pa11 h3 ld6_pa12 h4 ld9_pa15 h6 nvdd15 h7 qvdd h8 qvdd h9 qvdd h10 qvdd h11 qvdd h12 qvdd h13 qvdd h14 qvdd h15 qvdd h16 qvdd h17 qvdd h18 nvdd14 h20 usbotg_data5_pc7 h21 usbotg_data6_pc8 table 62. i.mx27 23 mm 23 mm bga (19 mm 19 mm)?signal id by ball grid location (continued) location contact name
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 137 package information and pinout h22 usbotg_data0_pc9 h23 usbotg_data2_pc10 j1 ld0_pa6 j2 ld1_pa7 j3 ld2_pa8 j4 ld4_pa10 j6 nvdd12 j7 nvdd12 j8 qvdd j9 gnd j10 gnd j11 gnd j12 gnd j13 gnd j14 gnd j15 gnd j16 qvdd j17 nvdd14 j18 nvdd7 j20 usbotg_data1_pc11 j21 usbotg_data4_pc12 j22 usbotg_data3_pc13 j23 usbh2_clk_pa0 k1 nfwp_b_etmtracepkt1_pf2 k2 nfrb_etmtracepkt3_pf0 k3 nfce_b_etmtracepkt2_pf3 k4 lsclk_pa5 k6 nvdd1 k7 nvdd1 k8 qvdd k9 gnd k10 gnd k11 gnd table 62. i.mx27 23 mm 23 mm bga (19 mm 19 mm)?signal id by ball grid location (continued) location contact name
i.mx27 and i.mx27l data sheet, rev. 1.3 138 freescale semiconductor package information and pinout k12 gnd k13 gnd k14 gnd k15 gnd k16 qvdd k17 upllvdd k18 nvdd7 k20 usbh2_dir_pa1 k21 usbh2_data7_pa2 k22 usbh2_nxt_pa3 k23 usbh2_stp_pa4 l1 nfwe_b_etmpipestat2_pf6 l2 nfale_etmpipestat0_pf4 l3 nfre_b_etmpipestat1_pf5 l4 nfcle_etmtracepkt0_pf1 l6 nvdd1 l7 nvdd1 l8 qvdd l9 gnd l10 gnd l11 gnd l12 gnd l13 gnd l14 gnd l15 gnd l16 qvdd l17 upllvss l18 nvdd13 l20 usbotg_data7_pe25 l21 usbotg_nxt_kp_col6a_pe0 l22 usbotg_clk_pe24 l23 usbotg_stp_kp_row6a_pe1 m1 d15 table 62. i.mx27 23 mm 23 mm bga (19 mm 19 mm)?signal id by ball grid location (continued) location contact name
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 139 package information and pinout m2 d14 m3 d12 m4 d13 m6 d11 m7 qvdd m8 qvdd m9 gnd m10 gnd m11 gnd m12 gnd m13 gnd m14 gnd m15 gnd m16 qvdd m17 rtcvss m18 rtcvdd m20 usbotg_dir_kp_row7a_pe2 m21 osc32k_bypass m22 power_on_reset m23 power_cut n1 d10 n2 d9 n3 d5 n4 d8 n6 d7 n7 d0 n8 qvdd n9 gnd n10 gnd n11 gnd n12 gnd n13 gnd n14 gnd table 62. i.mx27 23 mm 23 mm bga (19 mm 19 mm)?signal id by ball grid location (continued) location contact name
i.mx27 and i.mx27l data sheet, rev. 1.3 140 freescale semiconductor package information and pinout n15 gnd n16 qvdd n17 fpmvss n18 fpmvdd n20 sd3_cmd_pd0 n21 osc32vdd n22 osc32vss n23 extal32k p1 d6 p2 d4 p3 d3 p4 nc_p4_1 p6 ma10 p7 nvdd2 p8 qvdd p9 gnd p10 gnd p11 gnd p12 gnd p13 gnd p14 gnd p15 gnd p16 qvdd p17 nvdd6 p18 nvdd6 p20 ata_data0_sd3_d0_pd2 p21 ata_data1_sd3_d1_pd3 p22 sd3_clk_etmtracepkt15_pd1 p23 xtal32k r1 d2 r2 d1 r3 a13 r4 a12 table 62. i.mx27 23 mm 23 mm bga (19 mm 19 mm)?signal id by ball grid location (continued) location contact name
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 141 package information and pinout r6 nvdd2 r7 nvdd2 r8 qvdd r9 gnd r10 gnd r11 gnd r12 gnd r13 gnd r14 gnd r15 gnd r16 qvdd r17 fusevss r18 fusevdd r20 ata_data5_etmtracepkt13_pd7 r21 ata_data4_etmtracepkt14_pd6 r22 ata_data3_sd3_d3_pd5 r23 ata_data2_sd3_d2_pd4 t1 a11 t2 a9 t3 a8 t4 a7 t6 a1 t7 nvdd2 t8 qvdd t9 qvdd t10 qvdd t11 qvdd t12 qvdd t13 qvdd t14 qvdd t15 qvdd t16 qvdd t17 mpllvss table 62. i.mx27 23 mm 23 mm bga (19 mm 19 mm)?signal id by ball grid location (continued) location contact name
i.mx27 and i.mx27l data sheet, rev. 1.3 142 freescale semiconductor package information and pinout t18 boot2 t20 ata_data8_etmtracepkt11_pd10 t21 ata_data9_etmtracepkt10_pd11 t22 ata_data7_etmtracepkt12_pd9 t23 ata_data6_fec_mdio_pd8 u1 a6 u2 a5 u3 a4 u4 a3 u6 sd29 u7 nvdd2 u8 nvdd2 u9 nvdd2 u10 qvdd u11 nvdd3 u12 nvdd3 u13 sdcke1 u14 nvdd4 u15 nvdd4 u16 nvdd4 u17 avdd u18 avss u20 ata_data13_etmtracepkt6_pd15 u21 ata_data12_etmtracepkt7_pd14 u22 ata_data11_etmtracepkt8_pd13 u23 ata_data10_etmtracepkt9_pd12 v1 a2 v2 a0 v3 sdba0 v4 sd31 v6 a22 v7 gnd v8 gnd table 62. i.mx27 23 mm 23 mm bga (19 mm 19 mm)?signal id by ball grid location (continued) location contact name
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 143 package information and pinout v9 sd12 v10 sd6 v11 sd2 v12 dqm1 v13 sdcke0 v14 cs5_b_etmtraceclk_pf22 v15 nvdd5 v16 nvdd5 v17 mpllvdd v18 gnd v20 boot1 v21 boot0 v22 ata_data15_etmtracepkt4_pf23 v23 ata_data14_etmtracepkt5_pd16 w1 sdba1 w2 a25 w3 sdqs3 w4 sd27 w20 osc26m_test w21 osc26vss w22 osc26vdd w23 boot3 y1 sd30 y2 a24 y3 sd28 y4 sd26 y5 sd20 y6 sd17 y7 a19 y8 sd13 y9 sd9 y10 sdqs0 y11 dqm3 table 62. i.mx27 23 mm 23 mm bga (19 mm 19 mm)?signal id by ball grid location (continued) location contact name
i.mx27 and i.mx27l data sheet, rev. 1.3 144 freescale semiconductor product documentation 6 product documentation this data sheet is labeled as a pa rticular type: product preview, advan ce information, or technical data. definitions of these types are available at: http://www.freescale.com. 7 revision history table 63 summarizes revisions to this document since the previous release. y12 ras_b y13 sdclk_b y14 cs4_b_etmtracesync_pf21 y15 cs0_b y16 oe_b y17 pc_cd2_b_ata_diow_pf19 y18 pc_vs1_ata_da1_pf14 y19 pc_rst_ata_reset_b_pf10 y20 pc_poe_ata_buffer_en_pf7 y21 por_b y22 clkmode1 y23 extal26m table 63. document revision history rev. no. date significant change(s) 1.3 11/2008 ? in ta b l e 3 , ?i.mx27/mx27l signal descriptions,? switched fec_txd0 and fec_txd1 for sd3_cmd and sd3_clk. ?in ta b l e 2 3 , ?cspi interface timing parameters,? updated t6? and t13, and removed t14. ?in ta b l e 6 0 , ?i.mx27 24 mm 24 mm bga (17 mm 17 mm)?signal id by ball grid location,? changed ?rw? to ?rw_b.? ? added ta b l e 5 9 , ?i.mx27 full 17 17 mm package mapbga pin assignment.? ? updated ta b l e 6 2 , ?i.mx27 23 mm 23 mm bga (19 mm 19 mm)?signal id by ball grid location.? 1.2 7/2008 corrected part number in section 1.3, ?ordering information,? on p. 4. part number previously listed as mcimx27fvop4a has been corrected to read mcimx27vop4a. 1.1 7/2008 formatting and template work. table 62. i.mx27 23 mm 23 mm bga (19 mm 19 mm)?signal id by ball grid location (continued) location contact name
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 145 revision history this page intentionally left blank
i.mx27 and i.mx27l data sheet, rev. 1.3 146 freescale semiconductor revision history this page intentionally left blank
i.mx27 and i.mx27l data sheet, rev. 1.3 freescale semiconductor 147 revision history this page intentionally left blank
document number: mcimx27ec rev. 1.3 12/2008 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com freescale are trademarks or registered trademarks of freescale semiconductor, inc. in the u.s. and other countries. arm is the registered trademark of arm limited. arm926ej-s is a trademark of arm limited. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2008. all rights reserved.

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